generating pulse in VHDL

[grittinjames]

vhdl pulse

some one plz help in this problem
i having a 1 mhz clock,and a one hz clock


in each rising edge of 1 hz i want a pulse of 0.5us

how i can do it in VHDL
i tried a lot [/b]

 

[omara007]

pulse vhdl

First , do you want this design to be synthesizable or just a behavioral model ?

 

[grittinjames]

vhdl 1000ns pulse

i want synthesiZable

i tried but it creating bad syncronisation error

 

[ramanan.d]

vhdl pulse on rising edge

u can do it for getting a 0.5 s pulse by using a divide by 2 counter with a clok of 1hz......of if u wnt to get a pulse of 0.5 us u need to hav a higher frequency clock

 

[grittinjames]

vhdl pulse enlargement

check my first post i am having a 1Mz clock and 1 hz clock

in each rising edge of 1 hz 1 Mhz clock will be high

i just want my o/p to follow it once and come rest upto next rising edge of 1Hz

 

[nag123]

vhdl {pulse function}

You can try this one.
signal r1,r2,f1,f2,r_edge,f_edge : std_logic;

process(rst, clk_1Mz)
begin

if rst = '1' then
r1 <= '0';
r2 <= '0';
elsif rising_edge(clk_1Mz) then
r1 <= clk_1hz;
r2 <= r1;
end if;
end process;

r_edge <= r1 and not r2;

process(rst, clk_1Mz)
begin

if rst = '1' then
f1 <= '0';
f2 <= '0';
elsif falling_edge(clk_1Mz) then
f1 <= clk_1hz;
f2 <= r1;
end if;
end process;

f_edge <= f1 and not f2;

output_signal <= f_edge and not r_edge;

if 1hz signal is changing at the middle of the 1mhz pulse then there will be a definite delay b'coz the clock samples at the edges.

if you want to pulse without any delay you have to sample the 1hz signal with very high speed clock.

 

[avimit]

vhdl pulse design example

Well, that is a difficutl situation, but solutions are always there.
But before I paste the solution here:
I would like to warn you that you are tyring to generate 0.5 us signal using a 1us clock. Which in synchronous design rules, would not be possible, as the output would itself be a function of the clock. If you hare happy with it, then here is your solution:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY pulse_gen IS

PORT (
clk : IN std_logic; --1 MHz clock
OneHzSignal : IN std_logic;
pulse_out : OUT std_logic
);

END pulse_gen;


--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------

ARCHITECTURE rtl OF pulse_gen IS
SIGNAL OneHzSignal_del : std_logic;
SIGNAL pulse_sig : std_logic;
SIGNAL pulse_sync : std_logic;
BEGIN

p1: PROCESS(clk)
BEGIN
IF(rising_edge(clk)) THEN
OneHzSignal_del <= OneHzSignal;
pulse_sync <= pulse_sig;
END IF;
END PROCESS p1;

pulse_sig <= OneHzSignal and not(OneHzSignal_del);
pulse_out <= pulse_sync and clk;

END rtl;

 

[grittinjames]

pulse with delay in vhdl

hai nag 123

thanks for ur effort

but it is not working

i attached the simulated wave form

 

[grittinjames]

vhdl generating pulse

hai avimith itz not working

can u get at least 1us pulse in each rising edge of 1 hz clock

 

[nag123]

how to generate pulse in vhdl

there is a typing mistake in the previous code. replace f2 <= r1 with f2 <= f1 or
copy the following code.

change the output pulse AND equation as you need. See the attached waveform

library ieee;
use ieee.std_logic_1164.all;

entity ex is
port(clk_1Mz, clk_1hz, rst : in std_logic;
output_pulse : out std_logic
);
end ex;

Architecture rtl of ex is
signal r1,r2, f1,f2, r_edge, f_edge : std_logic;

begin

process(rst, clk_1Mz)
begin

if rst = '1' then
r1 <= '0';
r2 <= '0';
elsif rising_edge(clk_1Mz) then
r1 <= clk_1hz;
r2 <= r1;
end if;
end process;

r_edge <= r1 and not r2;

process(rst, clk_1Mz)
begin

if rst = '1' then
f1 <= '0';
f2 <= '0';
elsif falling_edge(clk_1Mz) then
f1 <= clk_1hz;
f2 <= f1;
end if;
end process;

f_edge <= f1 and not f2;

output_pulse <= f_edge and not r_edge;

end rtl;