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The single best way is to put the bandgap under a "poor boy
LDO" that shields the bandgap from the majority of supply
deflection. But this is less viable as Vdd approaches VBG,
more viable when you have more than VT(N)+VT(P) worth
of headroom.
Internal to the bandgap, try thing like making your local
loop compensation shunt decoupled rather than Miller
feedback (and return the decoupling to the rail that
helps more than hurts PSRR, case-wise). Adding some
selective cascoding at high impedance nodes such
that capacitive wrong-rail coupling is bucked and
critical current-setting devices are not perturbed,
helps too. These may look like worthless FETs in a
simple DC analysis but can stabilize bias point and
take that burden off the feedback loop.
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