[SOLVED] 100% success for CDC circuit or not?

To my opinion, it must 100% guarantee of success.
The circuit must make sure it meet the following accumption: T1_period > T_sync1_setup + T_sync0_meta_settle + T_wire.



If the Freq. of clk1 is very high, we must use another circuit to do the synchronization and make sure to meet the below equation.

More explain of CDC, you may refer to: Chapter 3: Common Used Hardware Architectures: https://www.udemy.com/course/digita...hitectures/?referralCode=365C67358DCDD5237CCD

Yes it is difficult to achieve the probability of failure to be 0. By very nicely synchronizing your design you just can reduce the probability of failure.
Design engineers just improve the failure rate from months to years or from years to decades depending on the synchronizing scheme used, but very difficult to say that the value is zero!

dpaul said:

Yes it is difficult to achieve the probability of failure to be 0. By very nicely synchronizing your design you just can reduce the probability of failure.
Design engineers just improve the failure rate from months to years or from years to decades depending on the synchronizing scheme used, but very difficult to say that the value is zero!

How adding flops in synchronizer help in reducing the prob. of metastability failure?

Hi All, I know this question has been asked in so many threads in one way or other. But still asking this. Please assume this is for discussion. And I am not looking for any proven mathematical equation or supporting documents. My motive is just to understand it. So question is as follows...

www.edaboard.com

Click to expand...

While I still insist that Digital circuit should achieve 100% success for synchronization point.

Please recall that: in a digital system, e.g. your computer, what’s the clk freq of it? How many different clocks there maybe? How many CDC points there may be in a chip? How may chips is installed in your PC?

So, even one CDC point with each failure of decades, how about the add up probability of all these CDC points?

And if we can make sure this equation is always true, why we can’t achieve 100% success?

you can not guaranteed if your design is 100% CDC clen , you will not get any failure because of it.
MTBF , can not be zero , although you can low the probability of failure by adding extra sync stage.

Nothing in this life is 100%. There even exists non-zero probability of a register spontaneously flipping from 1 to 0. RAMs and BRAMs also can flip bits. It is always a question of if it's "good enough".
When you use newer FPGAs fabricated with advanced production nodes and use high frequencies, the probability of metastability propagating through a register becomes large enough and it is advised to use 3 or 4 registers to cross clock domains:
clk1 reg -> clk2reg(meta) -> clk2reg(maybe_meta) -> cl2reg(stable)
or
clk1 reg -> clk2reg(meta) -> clk2reg(maybe_meta) -> clk2reg(maybe_maybe_meta) -> cl2reg(stable)

ILIA KALISTRU said:

Nothing in this life is 100%. There even exists non-zero probability of a register spontaneously flipping from 1 to 0. RAMs and BRAMs also can flip bits. It is always a question of if it's "good enough".
When you use newer FPGAs fabricated with advanced production nodes and use high frequencies, the probability of metastability propagating through a register becomes large enough and it is advised to use 3 or 4 registers to cross clock domains:
clk1 reg -> clk2reg(meta) -> clk2reg(maybe_meta) -> cl2reg(stable)
or
clk1 reg -> clk2reg(meta) -> clk2reg(maybe_meta) -> clk2reg(maybe_maybe_meta) -> cl2reg(stable)

Click to expand...

I agree that: Nothing is 100% guaranteed. Can we say: if the CDC circuit is designed properly, we can get same robustness as normal same clock domain sequential circuit.
And for your situation: synchronous to high Freq. clock domain. Besides the 3 or 4 stage Sync. DFFs, how about this circuit below:

That's a completely separate topic. What I was talking about is fighting metastability. There are other aspects - high to low frequency passage, passage of multi-bit busses and so on. They all have different reliable solutions depending on the type of signal crossed and specific conditions. I am not going to list them all.

Thanks for all your reply.
I think I have better understanding of CDC circuit now.
Thanks again.

"Metastability" is a continuum and if you slide clock
across data finely you will find a "magic" point where
(absent noise) the output never "snaps to", inside a
region of increasing delay (to infinity) and then just
missing the clock altogether. You do not get to know
where you will land, until much else is known, if you
are violating setup window (which is sandbagged).

The region around metastability thus affects what
the next stage will see, and blown-out delay has
the chance of putting the successor metastable
(or just wrong, data late), and on and on.

How much next-stage timing margin you have
goes directly to the odds. The half-cycle stagger
offers something, but the true metastable point
and some range close-in to it, could still eat that
all up and then some.

@fffish Can you please close this thread if your Q is answered?
Else new members joining after 1 year, trying to get a footprint here, will try to give the same answers in different ways later!