[10 Points] PLL bandwidth

[AdvaRes]

Hi members,

Can anybody help me understanding what does mean the term bandwidth in PLL ?

1- What does it stand for exactelly?
If we consider a PLL of 80 Mhz for exemple having a reference clock of 10 Mhz. Is bandwidth frequencies bellow 10 Mhz ? Bellow 80 Mh ?

2- It is said that PLL's bandwidth is determined according to the application.
Can someone explain by an exemple ?

I'll donate 5 pts for real help for each question.

Thanks in advance.

 

[rfsystem]

The loop bandwidth is typical a factor 5-100 lower than the reference frequency. In your example 2MHz to 100kHz.

The reason is that the PLL is a time-discrete but value-continuous system. Phase differences at the reference frequency are converted into charge steps. The update is only with the reference frequency. To filter the time-discrete charge packets you need some filter margin. Expensive implementations use higher order lowpass filters for the charge filtering.

The loop bandwidth could be quick estimated.

I assume that the chargepump delivers a current in proportion to the phase difference. For loop stability the proportional resistor in the loop filter define the transfer function around the loop unity gain.


Then the loop transfer around unity gain is:

H(s)=(2*pi*KVCO/s)*(1/DIV)*KCHP*R1

Units:

KVCO=[MHz/V], KCHP=[uA/rad], R1=[kOhm]


The Bandwidth is then

BW=KVCO*KCHP*R1/DIV

Take an example 80MHz VCO and 10MHz reference

KVCO=20MHz/V, KCHP=200uA/(2*pi), R1=5kOhm, DIV=8

BW=20MHz/V*200uA/(2*pi)*5kOhm/8=397.8874kHz

 

[AdvaRes]

Hi rfsystem,
thanks a lot for your elaborated reply.

In the relation
H(s)=(2*pi*KVCO/s)*(1/DIV)*KCHP*R1
I didnt get what part of the pll introduced R1.

Is R1 due to the filter ?

 

[rfsystem]

If the chargepump have current outputs...


C1: Integrating cap in series with
R1: Proportional resistor to bring loop phase back to -120° at unity gain (magic 60° phase margin)

Both C1 and R1 parallel to chargepump output

C2: Higher frequency filtering cap, again turn the phase back to -180°

The magic dimensioning is that the phase margin is about equal impacted by

T1=R1*C1

and

T2=R1*C2

by a factor a=T1*2*pi*BW and 1/a=T2*2*pi*BW

 

[AdvaRes]

Thanks Sir,
I guess you are talking about a filter like that.

How can we mesure T1 and T2 in the reponse curve ?

 

[fanshuo]

from the bode plot of the filter transfer function
you can find a zero and a pole
That is it.

I also have a question
is the 60 phase margin an optimum point?
Can I increase the phase margin further?

 

[rfsystem]

Hitting a magic 60° phase margin is a little ironic. In practice the dimensioning is dominated by tolerance analysis. You have to try to bring the phase margin into some window under component spread. Do not forget at this analysis the VCO gain change over voltage and dynamic excursions. So not only a full AC spread analysis but also a full transient stability and performance analysis under component spread is required.

 

[jecyhale]

Please refer this book. A very good book for PLL design.

Added after 4 minutes:

loop filter design. I have edit some equation for design loop filter.
Which can get about 60 degree phase margin
Wish it useful for you!