10-bit pipeline ADC at 6.75Mhz for imaging application ?

[pnanda65675]

pipeline adc timing diagram -patent

Tis is 1st time im handling ADC, i need to verify a 10-bit pipeline ADC which works at 6.75Mhz with 2.8V supply,currently im doing some study on the architecture & understanding the functionality of Pipeline. In general there is 2 signals in, video & reference which is goes to PGA and next to 10-bit ADC. i need to knw how to do some performance metrics test in Cadence for the ADC, such offest error,INL, DNL,SNR...i've a timing diagram of ADC, but thn im still vague & not clear...colud nybody explain in a way that makes me understand more about this...

 

[sunking]

tran. for offset ,INL, DNL
fft for SNR

 

[pnanda65675]

thanks sunking,

But do u get any idea on the timing diagram that i've posted.

 

[wsy979]

would u post an architecture diagram
let us kn more about ur pipelined ADC

 

[pnanda65675]

basically 2 signals in (i)video (ii) reference, and thn boost up using PGA before enter ADC. It has about 8 Clk cycle latency initially, but after that it starts sampling at 6.75Mhz converting analog signals continously. The dig. shown is just the preliminary stage, after that those signals goes to Digital Correction Logic before digital words out. The control signal in ADC are ACLK, CNVT,ADCBITS. The CNVT starts and stop the conversion process. Output interface signal will be DVAL,DCLK,SAMPCLK. First valid output appears at the ADCDATA[ 10:0] after CNVT goes high. This much only i understood abt the timing diagram, could nybody explain better for me to judge this timing diagram correctly.

 

[pnanda65675]

Nybody plz give me some response...its very much appreciated

 

[philipwang]

Why not read the product spec.? These signals wiil be described detailed in that doc.

Bg,

Nybody plz give me some response...its very much appreciated