10 Best ways to code an FSM in verilog/VHDL

[vipulsinha]

Hi All

I am looking for any material/handout that describes the best effective way to code an FSM.

Like HUffman method, 2/3 process method and the rtl for the each method.

Thanks
Vipul

 

[vivek_p]

One hot state encoding

 

[k12345k12345]

look into the following ....

h..p://www.asic-world.com/tidbits/verilog_fsm.html

there are a couple of papers at
h..p://www.sunburst-design.com/papers/

Added after 1 minutes:

also came across this ...
h..p://www.engr.sjsu.edu/crabill/vlogfsm.pdf

 

[mux_master]

Also here is another example how to make a state machine in verilog
**broken link removed**

 

[user_asic]

What about coding with case vs. if-else statements?

 

[mux_master]

All the examples in this thread use the case statement for the next state logic. I would say this is the preferred way to code this logic since it will synthesize to parallel logic. An if else structure on the next state logic describe a prioritized structure.

 

[amraldo]

Refer to Synthesis primer series books written by Bhasakr for VHDL and Verilog.
--
Amr Ali

 

[user_asic]

AFAIK, when using case statements, the end result is a large MUX for all the cases that have to do a lot of switching. Using if-else eliminates this because you don't build up a large MUX. Can someone confirm this?

 

[amraldo]

AFAIK, if-else if is equivalent to case statements logic wise. It depends on synthesizer manual how it will be synthesized.
--
Amr Ali

 

[user_asic]

But I think the fundamental difference is the size of the MUX which is synthesized.

 

[amraldo]

Yes, may be.
This is very synthesizer dependent.
BTW, it also depends on your coding style. Because some coding styles may add up some extra memories (latches, or FF's)
--
Amr Ali