10.7MHz to 4mhz divider schematic needed

neazoi · Dec 13, 2012

Hello, I need to make a frequency counter accurate to the Hz. I have made a quite accurate OCXO on 10.7mhz, but the frequency counter schematic I have found on the net uses a 4MHz crystal.
So I need a divider to divide down the 10.7mhz to 4mhz, since I do not know how to alter the code.

rohitkhanna · Dec 13, 2012

Sounds quite frustrating !!

Obvious options are -
a) alter the code. Do you have access to the code ? Do you have the necessary tools to alter it if you (or the forum members) knew how ?
b) alter your OCXO. If you made one, you can make another. This time for 4Mhz op
c) .... ?

Even in case (b), it might not work, since feeding a 4Mhz clock into whatever circuit you have *might* be different from connecting a 4MHz crystal.

keith1200rs · Dec 13, 2012

You could use PLL based frequency translators but they do create jitter https://www.idt.com/products/clocks...anslation/universal-frequency-translators-uft

The only one I have used is the ICS525 https://www.idt.com/products/clocks...-buffers/525-01-oscar-user-configurable-clock

Keith.

neazoi · Dec 13, 2012

Is there any way to do it with a simple frequency divider?

rohitkhanna · Dec 13, 2012

neazoi said:
Is there any way to do it with a simple frequency divider?

You mean divide by 2.675 ? Hmmmm..... anyone ?

keith1200rs · Dec 13, 2012

It can be done by counters if you don't care about the duty cycle by cycle dropping but I doubt that will have the desired effect where a consistent, stable frequency is required.

Keith

FvM · Dec 13, 2012

I suppose , the question can be answered by a)reading and b) thinking, preferably a combination of both.

Generally speaking a so called "fractional" frequency divider that selects 40 clock pulses out of 107 has an exact average frequency of 4 MHz. I presume you can imagine that it can be implemented by a purely digital ircuit, in contrats to a PLL that uses an analog voltage controlled oscillator,

But the fractional divider involves a jitter, or seen from a different viewpoint, it's output is spectrally impure. The effect depends on the nature of controlled circuit. In case of a frequency counter, it may increase measurement uncertainty, Gate times, that are a multiple of 10 µs, can be however exact.

rohitkhanna · Dec 14, 2012

FvM said:
.... Gate times, that are a multiple of 10 µs, can be however exact.

Its instructive to note how you got the 10uS period In essense, a gate based on any 40 cycles count will be an exact 10uS !:idea:
Unfortunately we have not been given the inner workings of the freq-counter, nor do we know what input frequency ranges the counter is designed for. Nevertheless a nice round & smallish number like 10uS is useful since its more than likely the designer chose some standard gate-times of 1mS/ 10mS or such-like.

So in essense we would need to set up a system to do a divide-by-2 for 27 cycles, and then no-divide for 53 cycles, and then divide THIS output again by 2 to square it up ?
That sounds like quite a lot of jitter/ spurs within an 80 cycle block.
Or is it better to do (3*27 + 2*13) /40 ?

neazoi · Dec 14, 2012

rohitkhanna said:
Its instructive to note how you got the 10uS period In essense, a gate based on any 40 cycles count will be an exact 10uS !:idea:
Unfortunately we have not been given the inner workings of the freq-counter, nor do we know what input frequency ranges the counter is designed for. Nevertheless a nice round & smallish number like 10uS is useful since its more than likely the designer chose some standard gate-times of 1mS/ 10mS or such-like.

So in essense we would need to set up a system to do a divide-by-2 for 27 cycles, and then no-divide for 53 cycles, and then divide THIS output again by 2 to square it up ?
That sounds like quite a lot of jitter/ spurs within an 80 cycle block.
Or is it better to do (3*27 + 2*13) /40 ?

The counter I am building is this one https://www.best-microcontroller-projects.com/frequency-counter-circuit.html
I do not think spurs would be so much of a problem, a bandpass filter could be used to reject many of these.
Not to mendion that the division from an already steady higher frequency oscillator would furthermore improve the frequency accuracy by the number of the division ratio.

FvM · Dec 15, 2012

I do not think spurs would be so much of a problem, a bandpass filter could be used to reject many of these.

Basically yes. Seriously speaking, the whole idea of 4 MHz frequency generation sounds like a dead-end to me, a bad solution for a problem that can be better solved in a number of different ways.

For the present problem, supplying the processor with 10.7 MHz clock would the obvious and straightforward way. When you say that you're not able to modify the code, how do you know that it meets your requirements at all?

I reviewed the descprition of the software project and found the below dubious description:

This file contains the gate loop time measurement routines - the loop time is tuned to 999us so that the caller can calibrate the 1 second delay time

In other words, the author didn't even manage to provided a state-of-the-art crystal accurate gate time generation for the PIC processor. Doesn't sound like connecting a precision frequency normal to it makes any sense.

neazoi · Dec 15, 2012

FvM said:
Basically yes. Seriously speaking, the whole idea of 4 MHz frequency generation sounds like a dead-end to me, a bad solution for a problem that can be better solved in a number of different ways.

For the present problem, supplying the processor with 10.7 MHz clock would the obvious and straightforward way. When you say that you're not able to modify the code, how do you know that it meets your requirements at all?

I reviewed the descprition of the software project and found the below dubious description:

In other words, the author didn't even manage to provided a state-of-the-art crystal accurate gate time generation for the PIC processor. Doesn't sound like connecting a precision frequency normal to it makes any sense.

Hm.... so basically this is not as accurate as I thought?
I am really new to microcontroller coding so I cannot do many things creating one my own.
Have you got any plans for an accurate counter (50mhz max) with preferably common cathode 7-segment display? I have not found any other 8-digit project using these displays

betwixt · Dec 15, 2012

The counter is fine, it's starting from 10.7MHz that's the problem.

You could just change the OCXO to a 4MHz crystal and trim it to exact frequency with a capacitor. If you need even more stability, you can temperature control a 4MHz crystal quite easily or you could lock it to an external frequency reference using a simple PLL arrangement.

Brian.

neazoi · Dec 15, 2012

betwixt said:
The counter is fine, it's starting from 10.7MHz that's the problem.

You could just change the OCXO to a 4MHz crystal and trim it to exact frequency with a capacitor. If you need even more stability, you can temperature control a 4MHz crystal quite easily or you could lock it to an external frequency reference using a simple PLL arrangement.

Brian.

Hm... it sounds easier to make another small oven for the internal 4mhz crystal or TC as you suggest, to avoid all this complexity, indeed.
Thank you all very much for your replies

rohitkhanna · Dec 15, 2012

neazoi said:
Hm... it sounds easier to make another small oven for the internal 4mhz crystal or TC as you suggest, to avoid all this complexity, indeed.
Thank you all very much for your replies

Oh good ! So we come full circle to my suggestion way up there in #2.
Good discussions though...

cheers!

neazoi · Dec 15, 2012

rohitkhanna said:
Oh good ! So we come full circle to my suggestion way up there in #2.
Good discussions though...

cheers!

Yes indeed, but now I (we) know why
Thank you

10.7MHz to 4mhz divider schematic needed

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