1 Second Clock using 25MHz clock

Status
Not open for further replies.
E

exgreyfox2

Newbie level 5
Joined
Mar 22, 2012
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,334
Hello,

I want to my an LED pulse on for 1 second and off for 1 second with Digilent BASYS board using the 25MHz clock. Here is my code but it does not seem to output anything to the LED. The idea is to count however many cycles of the 25MHz clock it takes to make 1 second and then reset the counter and toggle the LED on. q_out controls the LED.

Code: 
module Seconds_Clock(clk, count, q_out);
	input clk;
   output count;
	output q_out;
	
	reg [24:0] count;
	reg q_out;
	
	 always@(posedge clk)
		begin
			if (count == 25000000)
				begin
					q_out <= 1'b1;
					count <= 1'b0;
				end
			else
				begin
					q_out <= 1'b0;
					count <= count + 1;
				end
		end
	
endmodule

Thank you for any help.
 

In your code, q_out is high for one twenty five millionth of a second. You would never ever see a blink that short. Therefore the LED always looks to be off.

r.b.
 

Change to

Try inverting q_out something like q_out <= not q_out this way the led will stay on for 1 seconf and off another second
 

Thanks guys, yeah it hit me last night after i simulated this code that the led only goes high for a millionth of a second. If i use q_out <= ~q_out it will toggle on every clock cycle. What i want it to do is stay low until count reaches 25000000 and then reset the counter and go high and stay high for the same amount of time so to give the impression of a 1 second clock. but I have no idea on how to achieve this. Maybe an assign q_out = ~q_out outside the always block?
 

exgreyfox2 said:
Hello,

I want to my an LED pulse on for 1 second and off for 1 second with Digilent BASYS board using the 25MHz clock.
Click to expand...

Actually you almost got it. See below with minor changes.

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

module Seconds_Clock(clk, count, q_out);
    input clk;
    output reg q_out = 1'b0; // this makes sure the register gets a known state BOTH for simulation and actual hardware
    output reg [24:0] count = 0; // same story as for q_out
    
     always@(posedge clk)
        begin
            if (count == 25000000)
                begin
                    q_out <= ~q_out; // this toggles the q_out register every second. So you get 1 sec on, 1 sec off, etc.
                    count <= 1'b0;
                end
            else
                begin
                    count <= count + 1'd1; // note the 1'd1 .. this takes care of silly warnings about non-matching widths
                end
        end
endmodule



Incidentally, you are better of writing the module declaration something like this:


Code Verilog - [expand]
1
2
3
4
5

module Seconds_Clock(
    input clk,
    output reg [24:0] count,
    output reg q_out
);


That way you don't have to repeat yourself. ;-)

PS: I take it the counter as output of the module is for debugging purposes? If all you want is the 1 PPS, then you can keep counter internal to the module...
 

Ahhh thank you my good sir! I will give it a shot

 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…