0 ports layout in calibre LVS

[omar97]

Hello all,
I have a problem while using calibre LVS.
I am using icc2 as layout tool, TSMC 65nm as technology library, and calibre as lvs checker.
I showed that in Layout section there is no ports extraction and there is also unmatched nets that I suppose because of ports extraction reason.
I get 0 ports in layout.
I make a small design (Nor gate) and attach a screenshot to see this problem.
Can any one help me ?

--- Updated Jun 9, 2024 ---

This also a screenshot of another design (alu) that gives the same issue

 

[ThisIsNotSam]

your design should have 3 logical ports and 2 power ports. LVS cannot pass otherwise. Your layout has to be properly "annotated" to make sure the ports are recognized.