0.18u technology cadence tool

[vasu612]

cadence 0.18u

hi frenz,

can anyone who is using cadence tool for virtuoso can tell why there r 2 kinds of poly,,, when we use poly 1 & poly2 in r layout......?????


i've used poly1 in the layout but its giving some DRC error,, when i used poly2 instead of poly1 then DRC clean....why so.???


thankyou in advance.
vasvi

 

[pfd001]

0.18u technology

two polys are often used for capacitor. one poly is used as the gate, another one is only used for capacitor.

 

[safwatonline]

0.18 technology cadence

poly can be used to make gate , poly resistance and poly-poly cap. , each poly layer "i think" should be used for certain thing, u should refer to the PDK refrence for details about which poly is used for which thing,
i think that poly1 is used for gate and maybe resistors , while poly2 is used is used for caps. , note also that in caps the poly is required to be conductive as possible "ideally metal cap. which has infinte conductivity", while in resistors u want the resistor to be with low conductivity. " i think there is some special poly called HR (high resistance), but i am not sure , so u should refer to ur PDK to know which is he correct poly and to know also the rules for each layer.

 

[eng_Semi]

technology 0.18u details

which kit u r using ?
if TSMC, don't use poly2 layer.

 

[srivatsan]

poly2 layer cadence

For any given Process, there can be multiple choices of polysilicon level and metal levels. Usually, Poly-1 is used for resistor (both high and low values) and Poly-2 is used as Gate or Top-plate cap. If the total number of metals available is 5, then you can do layout using only 3; there is no need to use all the metal layers.

TSMC has multiple "flavors" within a Process Technology. Do not assume anything. Ask the concerned Prof/Technical Person.

Srivats