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sending serial data with respect to a clock in a test bench

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ananthan95

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Code: 
process (clk)
if falling_edge(clk) then
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
end if;

i want to execute the above set of statements in a test bench. that is, my clock will remain low for 640ns and I have to send my data in a 40ns interval(serial input, one after the other- 16*40 = 640). but the issue is that, wait statement will not work if i use a sensityvity list. what should i do?
 

You can try this code.
Code: 
process 
begin
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '0';wait for 40ns; 
adc <= '1';wait for 40ns; 
wait for <clk_period>;
end process;

In place of <clk_period> put your clock period (hoping your clock period is more than 640 ns).
 

sorry. I guess my question wasn't clear enough. I actually want to avoid giving manual delays. this clk is generated inside the code. so I want my data to go in automatically with the clock (without me providing the delay manually). the Ton of clock is 620 ns and T off is 640 ns. so when the clk is low, i want my data to go in serially. and it should stop sending data when the clk is high.
do you think creating another clock with 40ns Ton will help me in removing the wait statement inside the loop?
can I use both the clocks together so that it will run automatically?

in short instead of giving manual delays in the testbench, I want my data to go in serially according to the system clock when it is low.(16-bit data, each bit should stay high for 40ns)
 

This is what I use normally for testbenching

Code VHDL - [expand]
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signal a_slv : std_logic_vector(15 downto 0);
 
stimulus process
begin
  a_slv <= "1001111010100001";
  for I in a_slv'range loop
    if clk_low then
      wait until rising_edge(serial_clk); -- This could give strange occurance where clk_low goes high before re of serial_clk, in which case changes lines
      adc <= a_slv(I);
    end if;
  end loop;
wait;
end process;
 

Okk. then you can try this.
In the declaration
Code: 
shared variable i : integer := 0;
signal r16 : std_logic_vector(15 downto 0);
signal clk_40 ; std_logic;
and actual code will be
Code: 
process (clk)
begin
if (clk = '1') then
i <= 0;
elsif(rising_edge(clk_40)) then
adc <= r16(15-i);
i := i + 1;
end if; 
end if;
end process;
in addition to this you have input the value which you want to serially transfer in r16 (16 bit register) and declare one more process for clk_40 which is a 40ns clock.

I hope this will work.
 

I guess this is becoming a discussion on bus functional modelling.

@mjuneja that will not work. In simulation, processes only get executed when a signal in the sensitivity list changes. So with the code you posted, when clock changes '1' -> '0', neither option is valid. On '0' -> '1', then clk='1', so the i<= 0 ; is executed.

@ananthan. You cant mix sensitivity lists and waits. If you remember that processes are all started at time = 0 when there is no sensitivity list. so you can use @wesleytayler's example. But why not make a send procedure that can be used all over, and is easy to read whats going on?

Code VHDL - [expand]
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procedure send_data( d  : std_logic_vector; -- data to send
 
                    -- Signal interface
                    signal clk  : in  std_logic;
                    signal dout : out std_logic ) is
begin
  for i in d'range loop
    dout    <= d(i);
    wait until rising_edge(clk);    
  end loop;
end procedure send_data;
 
 
-- testbench
signal clk  : std_logic;
signal adc  : std_logic;
 
.....
 
-- Stimulus process
process 
begin
  adc   <= '0';
  wait until rst = '0';   -- do nothing during reset
  wait until rising_edge(clk);  -- synchronise with the clock
  
  send_data(x"DEADBEEF",         clk, adc);
  send_data(x"12345",            clk, adc);
  send_data(x"01234567890ABCDEF",clk, adc);
  
  wait;
end process;
 

I think I missed clk_40 in the sensitivity list so now this should work.
Code: 
process (clk,clk_40)
begin
if (clk = '1') then
i <= 0;
elsif(rising_edge(clk_40)) then
adc <= r16(15-i);
i := i + 1;
end if; 
end if;
end process;

Thanks @Trickydicky for pointing out.
 

Hi,

I ask myself: does it make sense to create such situation in a testbench?
I mean ... it is "unrealistic precise". Thus - I assume - it is not very useful to test for real world situations.

I don't know the real world situation, but often the "gating" is delayed by an unknown value...and the clock to data delay usually is unknown, too.

Klaus
 

wave_input.jpg
for a better understanding, the above pic describes my question. S1 and S2 are generated inside the code. I should give the 16bit data (D) serially with respect to any of the signal. and this process should repeat 24 time because i have 24 data points of 16 bit each. after sending in the 24th data it should start again from first data.

- - - Updated - - -

tb.JPG
this is how i do it right now using manual delay. the signal ADC_SDO is my data. other two are system generated signals
 

I'm not going to write the code, but you could do something like:

1) Detect falling edge of S1.
2) Use that detected edge to start a process that generates 16 cycles of S2.
3) Also use the detected edge to increment an index into your data array.
4) Use your S2 clock to shift your serial data

But I don't understand your aversion to using a wait statement. This is for simulation, right? Why make things harder??
 

Regarding #7.

What happens when you exceed the range with your I incrementation? You should constraint it.
 

wesleytaylor said:
Regarding #7.

What happens when you exceed the range with your I incrementation? You should constraint it.
Click to expand...

By the time range gets exceeded, clk will become '1' and 'i' will get reset to '0'.

As clk_40 has only 16 cycles in 640ns (i.e. when clk = '0') so only 16 bits will be transferred to 'adc' in that time.
 

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