can this passive mixer circuit reasonable?

Commonly，a passive is composed of 4 swithc. See Fig1

https://obrazki.elektroda.pl/54_1284133830.jpg

And usually it needs two voltage bias: One is at gate VB_G and the other is at source (or drain),VB_D. See Fig2

https://obrazki.elektroda.pl/0_1284133830.jpg



Theoretically voltage bias of VB_D can appears at drain or source.

For Zero-IF receiver, a low pass filter, such as GM-C filter, follows the mixer. Mixer is DC coupled to GM-C filter.
And the input common-mode voltage of the GM-C filter is usually at 1/2 VDD. This means VB_D can be applied by GM-C input bias.

Now problem comes:
When I design the mixer, how can I set VB_D.
After down-conversion, IF=0 Hz. If I set VB_D at the IF-side like Fig 2，on one hand, IF signal will flows from resistors R1 and R2 to ground. On the other hand, the two resistors R1 and R2 contribute extremely noise. I think the two resistor should not contribute noise. But why they do in my circuit?

I wonder how can I set the bias voltage VB_D and do not add extra noise?

I have read number of paper. Few supplied the bias circuit.

Thank you for anyone~~

The FETs are used as passive switches. The LO drives them from full on to full off. In effect they go from near zero ohms to nearly infinite ohms. This circuit was used in an IC by Siliconix many decades ago.

flatulent said:

The FETs are used as passive switches. The LO drives them from full on to full off. In effect they go from near zero ohms to nearly infinite ohms. This circuit was used in an IC by Siliconix many decades ago.

Click to expand...

Yes. This circuit has been used many decades ago.

I want to know how engineer build the bias circuit, because my circuit method introduces large noise.

Do you have any suggestion?