Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

synthesis of a design having clock domain crossing CDC paths

Status
Not open for further replies.
T

tariq786

Advanced Member level 2
Advanced Member level 2
Joined
Feb 24, 2004
Messages
562
Helped
67
Reputation
134
Reaction score
54
Trophy points
1,308
Location
USA
Activity points
3,050
Hi

I want to know how would you synthesize a design having multilple clock domains with clock domain crossing paths between the two clock domains.

What would be the constraints for CDC paths?

How would you verify the result of synthesis


Please reply thoroughly.

Thanks a lot
 

You need to use a create_clock for each valid clock input, check if there are some remaining clock pins not connected to define clock net.
In general, you need to define false path from one clock domain to other one clock domain.
RC (Cadence), apply this false path automatically if you used the -domain <unique_name> argument in create_clock command.
 
On the synchronizers, should a multi-cycle constrain be applied (beside the false path)?
 
The answer is "No" :)
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top