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Standcell development.

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googler123

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Hi All,

I want to know How to define the standcells and the Methodologies . Such as size ,performance ,R&C , extracted etc.

Thanks.
 

What do you mean of define standard cells?
Do you want to develop a new standard cell library (a new liberty file)?
 

thanks,

I have a standcells and I want to know the following things.

1.for example:NAND

I noticed they have several sizes type.such as N=1u/0.18,P=2u/0.18 or N=2u/0.18,P=4u/0.18.

How to define the sizes?? Just think about the min Length?

2.All the cells are the same H and difference width. How to define the Hight?

3.And how to simulate the setup time/hold on time /or raise time fall time?

thanks for your kindly reply.
 

Dear Googler
You have said that you have standard cell.
Do you have Liberty file (.lib) prepared for synthesis tools and ... or you have spice netlist of all cells such NAND ,NOR, INV , .... ?
If you have The spice netlists, The transistor sizes and structures of each cells are clear.
But if you have a .lib File, The file has not the information about circuitry of the cells.
In the Liberty file, There is plenty of tables of the data which say the delay, power of the cells in various conditions (inputs, ...).
Then after all, which of them do you have?
 

Standard cells will have same heights because if it differs we cant place it in the row of power and ground line... in the sense cells will be placed between power and ground stripes.. Look at the cell placement in the placement step of pnr u can see there may be double triple height standard cells(Its not same always)..... The thing is width may have any value but the height should be double triple etc..,

also for question 3 i cant predict what you are coming to convey...


It may help u.. thanks:razz:
 
Dear Oveis

I only have layouts,, missing schematics.and I would like to draw the schematics andha run LVS.

For LEF files, maybe I will generate by myself.but I donot know how to genrate the .lib and spice netlists.

Liberty file (.lib) use NCX?

Could you give some suggestions?


Thanks and Best Regards.

---------- Post added at 11:02 ---------- Previous post was at 10:56 ----------

Thanks,,

Good luck.

yadavvlsi said:
Min channel length is depends on which technology you are using. For example for 45nm technology you will find minimum channel length will be 45nm.

https://www.edaboard.com/threads/213826/#3
Standard cell characterization
Click to expand...
 

I think you should extract your layouts and with NCX or ELC (Encounter Library Characterizer) Generate a Library (.lib) file. Doesn't it?

---------- Post added at 11:04 ---------- Previous post was at 11:01 ----------

You can refer to this book.
It is so useful book in such flows.
41NepP3o33L._SL500_AA300_.jpg
 

OK,,

Get it..


Thanks.


Oveis.Gharan said:
I think you should extract your layouts and with NCX or ELC (Encounter Library Characterizer) Generate a Library (.lib) file. Doesn't it?

---------- Post added at 11:04 ---------- Previous post was at 11:01 ----------

You can refer to this book.
It is so useful book in such flows.
41NepP3o33L._SL500_AA300_.jpg
Click to expand...
 

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