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Inter chip would mean chip 2 chip. Intra chip IMO is what would be inside a chip between blocks.
There is no reason that distance by itself would be the reason for not meeting timing. The reason is usually because of
mismatched delays between clk and data signals.
all data at output should be flopped. All data received by a block should be immediately flopped. This helps you get enough setup time on your signals. Signal layout should be done properly so that clock and data arrive at same time.
thanks for the intra-chip clarification.
you mean that the solution will be in the backend flow.
if the signals going from one block to the second can be delayed for few cycles, then it will make backend life easier.
in this case I should define multicycles? or maybe use some conecting fifo between the 2 blocks to meet one cycle and keep it simple?
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