Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] [new1] verilog beginner

Status
Not open for further replies.
C

cloud9Z9

Newbie level 5
Newbie level 5
Joined
Dec 9, 2011
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,330
Code: 
/* Verilog for cell 'test1{sch}' from library 'testlib' */
/* Created on Thu Dec 08, 2011 18:43:01 */
/* Last revised on Fri Dec 09, 2011 01:01:37 */
/* Written on Fri Dec 09, 2011 01:10:29 by Electric VLSI Design System, version 9.00 */

module test1(A, B, C);
  input [0:2] A;
  output B;
  output C;

  /* user-specified Verilog code */
  wire [0:2] A;
  wire B;
  wire C;
  
assign C=A[0]|A[1];
  assign B=A[0]&A[1];
  
initial
  begin
  A[0:2] <= 3'b011;
  //#10;
  //A[0:2] <= 3'b111;
  //#10;
  //A[0:2] <= 3'b000;

  end
  
initial begin
  $monitor("OR=%b, AND=%b, IN=%b, time=%t\n", B,C,A[0:2]);
  end

endmodule   /* test1 */


Can somebody pls tell me wats wrong with my code?


test1.v:21: error: A['sd0:'sd2] is not a valid l-value in test1.
test1.v:12: : A['sd0:'sd2] is declared here as wire.
Elaboration failed


using iverlog compiler
 

You need to declare A as reg instead of a wire, since you are using it in a procedural block.
 

Hi!
(1) Inputs cannot be a reg data type - only wire. (2) Outputs can be both wire and reg.
As I see you are mixing a module description with a testbench... that's not good :wink:. Move initial blocks to a separate testbench file (for example tb.v) and instantiate your test1 module in it :

module tb;

reg [0:2] A;
wire B, C;

// instance of module test1
test1 UUT(.A(A),.B(B),.C(C));

initial
begin
A[0:2] <= 3'b011;
//#10;
//A[0:2] <= 3'b111;
//#10;
//A[0:2] <= 3'b000;

end

initial begin
$monitor("OR=%b, AND=%b, IN=%b, time=%t\n", B,C,A[0:2]);
end
Click to expand...

endmodule


-----------
also add following strings to the end of the first initial block:
#10;
$finish;
Click to expand...


Good luck!
 
Last edited:
Yeah.... I am sorry, I didnt go thru the code properly, and just posted the reply in a hurry. I didnt read properly and assumed it to be an output.

Sorry for the mistake on my part :)
 

Code: 
/* Verilog for cell 'test1{sch}' from library 'testlib' */
/* Created on Thu Dec 08, 2011 18:43:01 */
/* Last revised on Fri Dec 09, 2011 01:01:37 */
/* Written on Fri Dec 09, 2011 01:10:29 by Electric VLSI Design System, version 9.00 */

module test1(A,B,C);
  input [0:2] A;
  output B;
  output C;

  /* user-specified Verilog code */
  wire [0:2] A;
  wire B;
  wire C;
  
assign C=A[0]|A[1]|A[2];
assign B=A[0]&A[2]&A[1];
  
endmodule   /* test1 */


module tb;

wire [0:2] A;
wire B,C;
test1 UUT(.A(A),.B(B),.C(C));
initial
  begin
A[0:2] <=3'b101;
#10;
A[0:2] <= 3'b111;
#10;
A[0:2] <= 3'b000;
#10;
$finish;
end
  
initial begin
$monitor("OR=%b, AND=%b, IN=%b, time=%t\n", B,C,A);
end
endmodule

Pablo ~/Documents/Winter/copy/cp7/trunk/run $ iverilog test1.v
Pablo ~/Documents/Winter/copy/cp7/trunk/run $ iverilog tb.v
tb.v:6: error: Unknown module type: test1
2 error(s) during elaboration.
*** These modules were missing:
test1 referenced 1 times.


the test1.v compiled...but there seems to be something wrong with the tb.v file. Can pls tell me what is wrong? And A[0:2 ] are inputs so i should'nt be instantiating them as reg's right??
How do we include test1 file
Thanx for the quick reply.

---------- Post added at 16:34 ---------- Previous post was at 16:27 ----------

np...can u pls verify why my code isnt working below

---------- Post added at 17:12 ---------- Previous post was at 16:34 ----------

Isn't A[0:2] an input and since it is in procedural block, it has to be a reg type right but then u said inputs cannot be reg type?
 

Solved it thanx guys....A is declared as a register when it is used in the procedural statements and used a wire in combinational logic statements
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top