Adding Two Numbers In VHDL

Using IEEE packages:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

I want to add two numbers of bit length 8 and store the result into as an output of bit length 16. I am getting the following error when trying to compile my design:

# ** Error: D:/Profiles/w30239/My Documents/Miscallaneous/ECE 584/Project/Comp Instantiation Example/GoertzelAlg.vhd(33): (vcom-1272) Length of expected is 16; length of actual is 8.

How do I fix this error if I want to make sure my output (Xk0) is 16 bits but my inputs (x0,x1) coming in are 8 bits?

Thanks for your help!

Here is a snapshot of my code:

entity GoertzelAlg is
Port (x0,x1 : IN signed (7 downto 0);
Xk0 : OUT signed (15 downto 0));
end GoertzelAlg;

architecture Structure of GoertzelAlg is

begin

Xk0 <= x0+x1;

end Structure;

Actual length is 8, so you try to change Xk0 : OUT signed (7 downto 0));
Then there will be no error.


---------- Post added at 13:33 ---------- Previous post was at 13:25 ----------

Actual length is 8, so you try to change Xk0 : OUT signed (7 downto 0));
Then there will be no error.

you need to sign-extend the inputs. iirc, "resize(x0,16) + resize(x1,16)"

it is multiplication where the output is the combined length of both inputs (so 8bit x 8bit = 16). For addition you simply need an extra bit, and you can should do what permute suggests (sign extension before adding).