floating pin (Vdd) for ESD protection circuit

This is my proposed circuit for and ESD protection circuit. This is just a test circuit so I used
a load resistance first instead of the actual rectifier block. I did not place any Vdd since I
have read that it is the ESD voltage that biases the inverter circuit. Does this mean that the vdd
pin is floating?

I will really appreciate your insights! Thank you!

your idea is not quite right. you wont need vdd. i am not sure about an inverter with rc trigger. an nmos to shunt your current would be enough to pull net7 in case if esd. the net7 should be connected to pad.

It looks like a fairly ordinary triggered clamp but the problem lies in
the gain and speed, the clamp FET must actuate quickly enough to
protect the chip -and- have enough "hang time" to ride out the
HBM ESD source model's natural time constant, rather a whole
bunch of them since you're waiting for a few kV to be bled down
to a few volts.

Now I don't understand how you expect some 100nm transistor
to deal with the 6V input pulse....

steadymind said:

your idea is not quite right. you wont need vdd. i am not sure about an inverter with rc trigger. an nmos to shunt your current would be enough to pull net7 in case if esd. the net7 should be connected to pad.

Click to expand...

Referring to the schematic, aside from the connection of net7 to the MOS-connected diode, net7 should also be connected directly to the Vpulse , in this case?

---------- Post added at 22:12 ---------- Previous post was at 22:07 ----------

dick_freebird said:

It looks like a fairly ordinary triggered clamp but the problem lies in
the gain and speed, the clamp FET must actuate quickly enough to
protect the chip -and- have enough "hang time" to ride out the
HBM ESD source model's natural time constant, rather a whole
bunch of them since you're waiting for a few kV to be bled down
to a few volts.

Now I don't understand how you expect some 100nm transistor
to deal with the 6V input pulse....

Click to expand...

Thank you for that. But, the test circuit is just one of my simulated circuits where I used W=2000u and L=100nm since we're tasked to use the 90nm technology.
I've also tried other ratios and I'm planning to modify the W/L characteristics but I'm still struggling on how to compute for the correct transistor sizes.
Do you have any ideas for this?

You'd work from back to front. First off, your clamp device
needs to hold down some amps of current (Vbm/1.5K) at a
safe voltage. Assign the gate some tolerable voltage and
you can size by that. Bearing in mind that pins not directly
attached, will have to have some voltage allocated to the
ESD steering diodes (ring scheme) which lowers the allowable
clamping voltage at the core clamp.

Once the clamp size is set, the trigger taper can be sized.
You will have an "on" clamping voltage and you need to pull
in to that clamping voltage before breakdown and/or thermal
damage is accrued. Look at a simulated HBM (and/or other
threat waveform / source of interest) and the peak pin
excursion while waiting for trigger, against any foundry
transient overstress rules for gate ox, for a time bound.
This is what your front inverter has to smack the clamp
gate around, in. The inverter gain and trigger cap value
figure into this. If you have cap area then direct trigger
(Miller cap) is faster and more efficient, but often some
taper chain is more area efficient (though slower).