difference between verilog HDL & VHDL,

hi to all


what is the difference between verilog HDL & VHDL,from that most commenly used.



thanks advance

Check these links
Difference Between Verilog and VHDL | Difference Between | Verilog vs VHDL
verilog interview questions and answers: Difference between Verilog and vhdl?

Verilog is based on 'C' language where as Vhdl is based on Pascal and Cobol
Verilog is case sensitive
Verilog coding style is easier compared to Vhdl

From my experience verilog run faster on gate level simulation.

Click to expand...

There may be difference in synthesis quality with some design compilers, but I would contradict this statement as a general conclusion. If it happens, it's not related to the language itself.

how to answer this question? VHDL and verilog both are for RTL design , verilog is more like "C" syntax and different simulator may support different for VHDL and verilog!

Verilog is most used in the USA and VHDL is used mainly in Europe if I'm not mistaken. I think that Verilog is used by more companies than VHDL.

Verilog is a more user-friendly language, allowing code to be simpler. However, with this simplicity comes a slighlty increased risk of bugs when compared to VHDL.

VHDL is a strongly typed language, meaning that often you have to write a lot of code to do simple things. However, this also means a smaller probability of bugs in your design.

Personally I prefer Verilog because it is easier and the code is more readable. IMO the VHDL strong-typing brings more issues than it solves. Simple tasks like incrementing a variable, perform math operations, etc. often require long data type conversions in VHDL and a lot of code for simple multi-dimension array declaration. In Verilog is simpler, though not perfect. SystemVerilog brings the best of both Verilog, VHDL and C++ but some tools do not support it well.