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houly

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Hello,
I would want to design a simple current mirror with matched NPN transistors. The impedance of my load is a 50 ohm resistor and I would want a constant current of 3.6mA.
So I calculate the resistor to have the reference current which is R=(6-0.7)/3.6E-3 = 1.47k.

I do the simulation with simple 2N2222, but the result is about 3% missmatch, I was surprised of the poor matching of the circuit...
**broken link removed**
there is an error of 3.7% between the reference and the current of the load, is it normal ?

By placing resistor on the emitters it seems to be better but I don't know why, could you please explain ?

I also tried another classic circuit by placing a third transistor to sink Beta less current on the reference... but the result isn't better :

**broken link removed**
this give a 160µA missmatch => 4.2%

I hope that you could help me to better understand ...
 

I think you are not accounting for the difference in Vce. If you look at the derivation for the current mirror circuit in a book you will see that the ratio is not one to one, but it can be close. 4% seems good, I am assuming that you think the ratio should be 1 to 1. If you try to implement this in the real world things like tempco's will get in your way and 5-10% will be reasonable without any effort to correct the problems.
 
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    houly

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Early Effect. Such a deviation for a Vce difference of about 5 resp. 4V is quite normal, even surprisingly low. See this example (for quite a different BJT), where you'd get a mismatch of > 5% : View attachment Zetex_AN23_p6_Early-Effect.pdf
 
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Hello Erikl, cmontoya,
Thanks a lot for your replies and the link, it may be helpful to better understand current mirror and the early effect of the transistor.
For the Early effect, I only remember that the collector current grows up with the Vce instead of a straight line characteristic. But is it the Early effect that affects the performance of the second schematic ? I mean that since the transistor help the reference current transistor to provide a little current to the base of Q1, I suppose that the current on base would be very close on the Q1 and Q2 and therefore the collector current too, but I surprised by the result of the simulation, it doesn't seem to improve at all ! Do you think it's early effect that affect the performance of the second
Cmontoya, I need to improve the stage and implement (you're right) tempco but I don't really have experience in it, do you have any book or application note that could help me to implement tempco for this kind of circuit ?
Thanks a lot for your explanations.
 

houly said:
... is it the Early effect that affects the performance of the second schematic ? I mean that since the transistor help the reference current transistor to provide a little current to the base of Q1, I suppose that the current on base would be very close on the Q1 and Q2 and therefore the collector current too, but I surprised by the result of the simulation, it doesn't seem to improve at all ! Do you think it's early effect that affect the performance of the second
Click to expand...

Sure! Your VBE generating transistor Q2 has a VCE≈1.26V , whereas your mirror transistor Q1 has VCE≈5.8V . Early effect!
 
Hello Erikl,
Thanks a lot for your help, you're right it's the early effect :)
 

Right. If you want less deviation, you have to care for most possible equal VCE voltages of the current generating/limiting transistors. This calls for a few more transistors, s. e.g. below:
current_mirrors.png
 
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Hello Erikl,
Thanks a lot for your schematics, I also tried with resistors placed on the emitters to reduce the VCE voltage, it seems to work. I didn't try yet your examples, but I'm very interested in your schematics, I will feedback you soon if I don't understand the behaviour of the added transistors.

thanks a lot
 

I also tried with resistors placed on the emitters to reduce the VCE voltage.
Click to expand...
The main effect of additional "degeneration" emitter resistances is feedback, among others increasing the output resistance and thus reducing the Early effect.

You didn't mention the actual objective of your experiments. If they are targetting to real circuit design, you also should think about real transistor parameters, e.g. expectable transistor matching and available components in the respective technology. Availiability of precise resistors may be e.g. limited. In a discrete transistor design, all matching attempts are void anyway.
 

Hello FvM,
I have to design a low noise design to bias a photoconductive sensor. I would compare the performance of a simple resistor polarisation (regulator to provide low noise voltage source and resistor to apply the wanted current in the sensor) and a current generator (like a current mirror) to minimize the noise from the polarisation stage.

I have MAT12 transistors to test this architecture (and I hope have the PNP (MAT03) version soon). I would also want to test this 2 stages transistor pair configuration like this :

​

This permit to provide a better noise immunity from the supply rails, I don't know if it's relevant for noise which come from the transistors added for this architecture.

It's only an idea, I didn't test it and didn't yet implement the improvement to correct the Early effect on this architecture.
 

This permit to provide a better noise immunity from the supply rails, I don't know if it's relevant for noise which come from the transistors added for this architecture.
Click to expand...
The ambiguity of the term noise may be a problem here. If you're operating near sensor noise limits, transistor noise will be most likely a serious problem, and a strong point against basic current mirrors as bias sources. Degenerated current mirrors can perform better, simple load resistors operated with sufficient voltage are probably superior.

I suggest to get an overview of individual noise source's contribution in a SPICE noise analysis, or peform a hand calculation considering basic noise relations of semicoductor circuits.
 

Well, I'm very interested in hand calculation of the noise for this kind of circuit because I'm not very familiar with transistor noise equivalent circuit and it could be a very good exercise to learn how I can do to calculate it. Could you please help me to define the equivalent noise circuit for the last architecture ?
 

You need to consider transistor shot noise for a first order estimation. Secondly base resistance and flicker should be added. For low frequencies, flicker (1/f) noise can be severe.
 

Hello,
I'm going to do the analysis by hand with the first order estimation but I have a question about noise simulation for this kind of circuit (no input, only output) Pspice ask me a source for the noise analysis, how can I do ...?
 

houly said:
Pspice ask me a source for the noise analysis, how can I do ...?
Click to expand...
For your above shown schematic I'd suggest to use the center tap of your R5 (use two 1.5k resistors in series).

BTW: Your schematic doesn't resolve the current deviation due to the early effect, but I think this shouldn't be your main priority. Why -- do you think -- these currents should be equal at all?
 
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Pspice ask me a source for the noise analysis, how can I do ...?
Click to expand...

In this, case, I would place an equivalent circuit (a resistor with a series voltage source) for the photoconductive sensor. The noise quantities can be calculated then referring to this voltage source. Without a sensor representation, you can place an AC current source parallel to the circuit output.
 
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In this, case, I would place an equivalent circuit (a resistor with a series voltage source) for the photoconductive sensor
Click to expand...
In this case, what does the voltage source represent ? is it just to have a voltage reference to deduce the noise contribution of the stage ? what is the voltage value could you suggest me ?
 

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