IO Timing analysis : how to resolve timing issues?

What to do if a timing violation occurs? Should all the paths be constrained? what to do if i see a path as unconstrained?

Well, it is very general question. It depends on type of timing violation. Please provide the log where the violation log can be seen.

Hi,

at what stage you are getting violations? before CTS or after?

regards,
Subhash

I'm getting it after CTS. What I understand is, the only 3 ways to remove violations is :
1. by replacing the driving cell with another cell with more capacity
2. place the cells close by
3. apply buffers in the clock path


Please let me know if I am right. and also suggest if there are any more ways to improve timing. I'm not doing the PD. I just need to analyze and give feedback to the PD team. So, I don't understand too much of PD terms.

hello,

If the violation is for the timing path reg to reg,
increase the driving cell strength.
avoid to put buffers in the clock path, if u do, there are chances for another timing path will get violations.

If the violation is for the IO timing path (reg to output or input to reg),
u can apply any of those methods u mentioned.

As far as I know, these are only the ways to improve timing.

regards,
Subhash

yes. it's on IO timing path. So, inserting buffers on clock path also is possible right?
I was just curious to know what can be the reason for using inserting buffers in clock path if it's IO path and not using on reg-reg path. Is it because, if buffers are inserted on clock path at the boundary, it'll affect the whole design equally?

IO timing path:
In IO timing paths inserting buffer means you are placing the IO port far away so that data will reach in the required time. Due this you may close the timing, but the problem is for PD team. They have to perform routing and CTS again.

reg to reg timing path:
You can aslo perform inserting buffers in clock path. If you do this, the next timing path may get violated and there are chances to get hold violations in the same path also. So, inserting buffers is the problem for STA guy. In this case aslo PD team has to perform routing and CTS again.

So, as far as I know, we have to play maximum with data path only. For Setup, increase the driving strength of the cells so that the delay gets decreased and for Hold, insert the buffers so that the data path delay will increase. If you are not able to close timing with this, take the help from PD team and proceed.

In previous message you mentioned that placing the cells colse by is also one technique.
You (timing closer guy) can't place the cells close by, right?
PD team will place the cells and from that team we will get spef file, using this we perform timing analysis. We can't play with the placement of cells.

If I am wrong in any case, let me know.
If you know more information, share here.

regards,
Subhash