zxvc
Newbie level 5
IC Compiler & SRAM/Macro Pin Min Area Problem
I have a design with SRAMs (macros).
Each logical pin of the SRAM has three physical pins (draw by metal1-3.)
I use IC Compiler for APR my design.
Unfortunately, after routing, the min area DRC errors are generated at locations of SRAM pins.
The problem comes from:
IC Compiler doesn't use all pins of SRAMs for connections but only one of three physical pins of each logical pin.
Thus, the unused physical pins violate the min area errors.
How do I solve this problem?
I have a design with SRAMs (macros).
Each logical pin of the SRAM has three physical pins (draw by metal1-3.)
I use IC Compiler for APR my design.
Unfortunately, after routing, the min area DRC errors are generated at locations of SRAM pins.
The problem comes from:
IC Compiler doesn't use all pins of SRAMs for connections but only one of three physical pins of each logical pin.
Thus, the unused physical pins violate the min area errors.
How do I solve this problem?