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two-stage OP DC voltage at its inputs: presim versus post-sim

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allennlowaton

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I did a post-simulation with my OP alone. I found out that there's a 20mV~30mV DC difference on its inputs. The gain is not anymore positive. Further simulation shows that the said OP can only afford to have 2mV DC difference on its inputs. How can I improved my OP to obtain such requirement?

---------- Post added at 09:34 ---------- Previous post was at 07:52 ----------

this is the circuit in which the post-sim results being obtained from

65_1320741272.jpg
 

How did you match the MN3 and M2?
How did you match the input differential transistor of the OP1?
 
I only showed M2 in the figure, as a matter of fact there are other three branches (M3, M4, and M5) in my circuit.
With that I used this matching style;



For the input pairs of the OP1, I used

AB
BA
 

I'm confused about the circuit. It shouldn't be so much mismatch with this matching style.
So i think you should check the OP1. Is the gain or driving force of the OP1 enough?
As your picture shown, the ML1 is used as power mos. isn't it?
So i think it's large amount of mosfet.
 
Last edited:
I checked the post simulation of a stand-alone OP, when the difference of the DC inputs ranges from 20mV~30mV. The gain is already negative. How can I improved my OP? ML1's device size is 500u.
 

allennlowaton said:
I checked the post simulation of a stand-alone OP, when the difference of the DC inputs ranges from 20mV~30mV. The gain is already negative.
Click to expand...

The gain is negative just because the input voltage has 20mV~30mV difference.
please tell me the structure and the bias current of the OP1.
And you can add a cap to your schematic between the OP1 output and the gate of ML1, which is about 5~10pf. Then you can run a simulation, tell me the result.
 
Last edited:
I don't have a problem during the PRESIM. The 20mV~30mV difference has been found on the POST-SIM.
The OP is a two-stage and the bias current is 4uA.
 

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