Doubt regarding CMOS fundamentals

Hi

can anyone tell me what is body effect in CMOS?
and what is meant by process in PVT conditions..

thanks in advance

Hi Sharif,

For a CMOS configuration, the source of Pmos and Nmos should be connected to power and gnd respectively. This is when you are talking of one Pmos and One Nmos transistor as is the case in an Inverter.

But when you have multiple transistors as in the case of a 2 i/p Nand Gate where in Pmos are in parallel and Nmos(N1 & N2) are in Series...The drain of N1 is from where you obtain the output and the source of N1 will be connected to drain of N2(since a series config). The source of N2 is connected to gnd.

Now there will be no problem with the N2 switching/Vth values as its source is connected to Gnd. Now think of N1 whose source should be connected to Gnd but instead connected to drain of N2. For proper maintenance of switching/Vth for N1, its source should be maintained at Gnd but as it is connected to drain of N2 it may see some voltage above gnd..resulting in a change of threshold voltage..This change in Vth because of the series connection of two transistors is called as Body Bias effect.

For a Pmos transistor its the same when its Source is not connected to Vdd.


Hope it clarifies,

cheers,

sharif.shiek said:

Hi

can anyone tell me what is body effect in CMOS?
and what is meant by process in PVT conditions..

thanks in advance

Click to expand...

Check the below link for a brief description of process, voltage and temperature variations,
ASIC-SoC-VLSI Design: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis

It is known that a MOS transistor with the source-body voltage different from zero has the threshold voltage modified by the body effect, that is if $ V_{sb}\neq 0 $, with $ V_{sb}$ the source-body voltage (let's remember that for a n-MOSFET $ V_b = V_{SS}$ and for a p-MOSFET $ V_b = V_{DD}$), then $ \vert V_{Th}\vert _{V_{sb} \neq 0} > \vert V_{Th}\vert _{V_{sb} = 0}$. The initial conditions of the chain nodes are set by the initial condition on the output. So if the output node is discharging, then one (and only one) n-MOSFET is switching from off to on. It means that all the other MOSFETs are already on, and while the starting voltage of the output node is $ V_{DD}$, all the internal nodes have as a starting voltage $ V_{DD} - V_{Tn}^{*}$.

With the notations of previous paragraphs, the N-th (topmost) n-MOS transistor has $ V_{s_n}^N = V_{DD} - V_{Tn}^{*}$, with $ V_s$ source potential and $ V_{Tn}^*$ the threshold voltage modified by the body effect. All the internal transistors have $ V_{d_n}^i=V_{s_n}^i=V_{DD}-V_{Tn}^* $, while the first one has $ V_{d_n}^1=V_{DD}-V_{Tn}^*$ and $ V_{s_n}^1=0$.

The threshold voltage variation as a function of $ V_{sb}$ is given by:

$\displaystyle \Delta V_{Tn}=\gamma(\sqrt{2\vert\Phi_p\vert+V_{sb}} - \sqrt{2\vert\Phi_p\vert})\; ,$

with $ \gamma= \frac{\sqrt{2\varepsilon_s q N_a}}{C_{ox}}$ and $ \Phi_p = -\frac{KT}{q}\ln{(\frac{N_a}{n_i})}.$

The source potential of the top transistor is

$\displaystyle V_s = V_{DD}-V_{Tn}^*\; ,$

and, if $ V_{Tn0}$ is the threshold voltage with $ V_{sb}=0$, then $ V_{Tn}^*=V_{Tn0}+\Delta V_{Tn}$ and we can solve for $ V_{sb}$:

\begin{displaymath}\begin{split}V_{sb}&= \pm \frac{\gamma\sqrt{4\gamma\sqrt{2\ve... ... + V_{DD} - V_{Tn0} + \frac{\gamma^2}{2} \quad (>0) \end{split}\end{displaymath}

Process is the status during semiconductor fabrication in Fabrication laboratory.