PROGB pin and INITB Pin in Spartan 3A XC3S50A

Hi,

I am planning to design an hardware for Spartan 3A (XC3S50A). Can anyone tell me what this ProgB pin and INIT_B pin can be done in the hardware design. I had seen the timing diagram for the same. I had attached the same also. Can any one tell me how we can achieve this timing waveform using the external circuitry to ProgB and INITB pin?
Please let me know.


Regards,
V. Prakash

https://obrazki.elektroda.pl/79_1319173959.jpg

You should have a look at this document from Xilinx UG332.PDF (https://www.xilinx.com/support/documentation/user_guides/ug332.pdf)
From a (really quick) look, the PROG_B is an input (and could be fixed to '1', or even left unconnected I think because it is 'internally' pulled up), and the INIT_B is an output indication. So, you don't need anything 'to achive' for these pins.
In the UG332.PDF are the different methods described on how to 'program' the Spartan.

Now keep in mind (relating to your other post about your RAM requirements) that the S50 has 54 kBits block RAM. These block RAM are actually blocks of 18-Kbit (2048 kByte), so the S50 has three of these.
It can be that the total memory of the S50 suffices, but that you need (as example), 5 * 1024 kByte blocks. I'm not absolute sure that in this case the (three) block RAMs of the S50 can be divided up that easiliy. It is by definition easier to work with single block RAM's without the need to divide them up. The IP cores from Xilinx allow to 'fabricate' very nice constructions with block RAMs, but it might not be possible to divide them up in smaller pieces.
Therefore the suggestion in the other post, about using the ISE, and start designing is the best way to go. You can already start implementing your (software) design before deciding about the hardware at that point. Just try implementing it with the S50 device, and if it fails you know you have to use another device (or use another strategy/different resources to get it fit). The S200 would do in any case (it has 16 block RAMs of 18-kBit).

Hi;
FPGA PROG_B pin is related to its configuration.
I mean when prog_b goes from low to high FPGA clears INIT_B, DONE signals and the internal logic, and then samples the mode select gpios M[2:0] (At this time init_b goes high, so mode select gpios should be stable and desired value at the moment).
Then FPGA reads from flash and reconfigures itself, then the indicator pin DONE goes to high.
So you don’t need to apply anything on prog_b and init_b signals in normal conditions.
You can consider prog_b as a hardware reset pin to FPGA. If you need, you can adjust boot up timing applying a small RC cct on the prog_b. (ie wait until all supplies to be stable)
If you pull prog_b or init_b low, FPGA will not configure itself as far as they are in low logic.
Please also have look at this;
https://www.xilinx.com/support/documentation/user_guides/ug332.pdf

Hi,

I will keep the Progb pin pulled up. and INIT pin as open. some threads telling that PROGB pin is equal to reset pin of FPGA. so we have to reset the fpga using some rc circuit or supervisory circuit to configure the FPGA. so i had some doubts in it.
Progb pin = pulled up using an resistor
Initb pin = open. ? will it be ok?

Regarding the ram selection, thanks for letting me know this. xilinx will not allow the block ram to divide in smaller pieces?
suggested XC3S200A is the BGA package, there is no inhouse provision for BGA. have to go with TQFP package.

Thanks,
V. Prakash

... xilinx will not allow the block ram to divide in smaller pieces?
I'm not sure.

But, your are not restricted to using block RAM. There is also distributed RAM. Xilinx also has some nice IP cores, of which one can generate RAM blocks from distributed memory.
Just try implementing your design in the ISE and try out.

The S200 is also available in 144-pin Thin Quad Flat Pack (TQFP) TQ144/TQG144

Hi,

Both spartan3a: XC3S50A(TQFP 144) and XC3s200A (TQFP 144) are pin compatible? Please let me know.

I am attaching the tq144 footprint and also the package details of spartan 3a. Please let me know both are pin compatible. if S50 wont support, we can replace s200 in the same footprint. I/O's are common?


thanks,
V. Prakash


https://obrazki.elektroda.pl/26_1319263208.jpg
https://obrazki.elektroda.pl/24_1319263208.jpg

I see I made a mistake. I took the Spartan-3 instead of the Spartan-3A.

However, the XC3S50A and XCS200A are both available in a VQ100/VQG100 package, which are pincompatible (some minor differences in differential signal assignments), so you can use either the S50A or S200A.
See this document DS529.PDF (www.xilinx.com/support/documentation/data_sheets/ds529.pdf).
Look at page 5 (overview devices/packages), and page 70 (differences S50A/S200A VQ100 package).

Hi,

I need a I/O 's of minimum 80 for my application. So i choosen the TQ144 package instead VQ100

thanks,
V. Prakash

Then only the S50A is an option I guess from this family.

You could use another Spartan family:


Spartan-3E
XC3S100E 15K 72K (Distributed/Block RAM)
XC3S250E 38K 216K
Spartan-3 ('mature/discontinued' product)
XC3S50 12K 72K
XC3S200 30K 216K
XC3S400 56K 288K

For reference:
XC3S50A 11K 54K

Since the Spartan-3 is 'mature' I would opt for the Spartan-3E. You can use the XC3S100E or XC3S250E (pincompatible).
See DS312.PDF (www.xilinx.com/support/documentation/data_sheets/ds312.pdf)

I just designed a board with a XC3S50AN. It is the same as the XC3S50A but with an internal flash. At XC3S50AN is important to keep PROG_B pin low duing some time to get the power rail stable due to the internal flash initialization. The best way is to use an external reset ic as a MAX803/MAX809. A RC circuit will also work. On XC3S50A i am not sure if you will have this problem due to the external flash. You should ask on Xilinx forum, they can proper answer you about that. Is always good to place a led at INIT_B pin to make sure that the FPGA initialized ok. Take a look at the User manual to see all the possible configurations of the INIT_B. If you are using a single FPGA i would go for drive_done configuration. No, BLOCK RAMs can't be divided and thats horrible. Aaltera M4K are much more flexible. Dont rely on the distribuited RAM. It is not an extra resource, it is just an extra feature that you configure your LUT as an RAM. So bascally you are going to be using your normal logic resource, and on a 50K gates FPGA is not much. As sugested, create your design and check if it will fit on the FPGA, it is the best way to go. You alwas have other vendors if it does not fit. An example is EP1C3 that is more expensive, but available on 100 pin package and with more than the double of resources of the XC3S50A.

Cya

Hi,

Thanks. I will try to go with Spartan 3E family.

Thanks,
V. Prakash

---------- Post added at 13:23 ---------- Previous post was at 11:36 ----------

Hi sink0,

The in-system flash of XC3S50AN is 1Mbits. This in-system flash = External EEPROM.
Please let me know.

thanks,
V. Prakash

Because the XC3S50AN has in-system flash, you don't need an external 'source' for the FPGA 'program'. It is all contained in the FPGA itself.

Hi,

couldnt understand clearly. Actually i planning to interface External EEPROM with XC3S50A to store the data. If XC3S50AN has in-system flash(EEPROM), then i can go with this 50AN chip. If i am correct, whatever the logic return in the FPGA--> XC3S50AN will not be erased during power OFF/ON.? Please correct me if i am wrong.

you don't need an external 'source' for the FPGA 'program

Didnt understand clearly. Can you explain in details.?


Thanks,
V. Prakash

I strongly advice to read the datasheets Xilinx provides. All the answers given here are taken directly from these datasheets! No magic/experience here. Just some basic reading.

You don't need an external EEPROM/Flash/SPI (== 'source'), as is typical with the usual range of FPGA's. The XC3S50AN has this on-board. During power on this on-board flash is loaded in the RAM of the FPGA.

From the datasheet:

The FPGA’s configuration data is stored on-chip in nonvolatile Flash
memory, or externally in a PROM or some other nonvolatile
medium, either on or off the board. After applying power, the
configuration data is written to the FPGA using any of seven
different modes:
•
Configure from internal SPI Flash memory (Figure 2)
•
Completely self-contained
•
Reduced board space
•
Easy-to-use configuration interface
•
Master Serial from a Xilinx Platform Flash PROM
•
Serial Peripheral Interface (SPI) from an external
industry-standard SPI serial Flash
•
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
•
Slave Serial, typically downloaded from a processor
•
Slave Parallel, typically downloaded from a processor
•
Boundary-Scan (JTAG), typically downloaded from a
processor or system tester




In-System Flash Memory
Each Spartan-3AN FPGA contains abundant integrated SPI
serial Flash memory, shown in Table 3, used primarily to
store the FPGA’s configuration bitstream. However, the
Flash memory array is large enough to store at least two
MultiBoot FPGA configuration bitstreams or nonvolatile
data required by the FPGA application, such as
code-shadowed MicroBlaze processor applications.

Hi,

Thanks. I am Planning to interface the SPI serial flash memory 128Mbit (part number: spansion S25L128P0XNFI001).
with Spartan 3A XC3S50A. If i choose XC3S50AN, there is no need of this serial flash. Please let me know.


Thanks,
V. Prakash

"If i choose XC3S50AN, there is no need of this serial flash. Please let me know."
Correct, the in-system flash replaces the external flash. Basically they combined a typical FPGA and flash memory using an internal SPI interface.


The datasheet says it all www.xilinx.com/support/documentation/data_sheets/ds557.pdf:

After configuration, the FPGA design has full access to the
in-system Flash memory via an internal SPI interface; the
control logic is implemented with FPGA logic. Additionally,
the FPGA application itself can store nonvolatile data or
provide live, in-system Flash updates.

In-System Flash Memory
Each Spartan-3AN FPGA contains abundant integrated SPI
serial Flash memory, shown in Table 3, used primarily to
store the FPGA’s configuration bitstream. However, the
Flash memory array is large enough to store at least two
MultiBoot FPGA configuration bitstreams or nonvolatile
data required by the FPGA application, such as
code-shadowed MicroBlaze processor applications.

"If i choose XC3S50AN, there is no need of this serial flash. Please let me know."

Nono, you need the external serial flash.

Mmmh, I see that contradicts Marcel Majoor's post. Oh if only there was some way to find out which is correct!

Well, the XC3S50AN has onboard flash, so you don't need an external flash.

See www.xilinx.com/support/documentation/user_guides/ug332.pdf

If you want to be on the safe side, you can always allow the option of an external flash, but it is not needed.
You can also have a look at the Spartan-3AN starter kit schematics/user-guide.

Configuration Mode
Mode Pins
M2:M1:M0
FPGA Configuration Image Source
Internal Master SPI ---->
Spartan-3AN Starter Kit Board only! This
mode configures a Spartan-3AN FPGA
using the internal In-System Flash memory.
This mode is not supported on the
Spartan-3A Starter Kit board.

Nono, I maintain prakashvenugopal needs the external flash.

I guess there's nothing else for it but prakashvenugopal checking it in the datasheet.

Hi mr.flibble,

If i select Spartan 3AN XC3S50AN, i need a External Serial flash? Please confirm. I am in the process of board design.

Regards,
V. Prakash