Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Difference in delays of NAND and NOR

Status
Not open for further replies.
S

senmerida

Junior Member level 3
Junior Member level 3
Joined
Oct 15, 2011
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Bangalore
Activity points
1,438
Why is there a more DELAY for NOR when compared to the NAND gate.
ie
Tphl(NAND)< Tphl(NOR)
 

senmerida said:
Tphl(NAND)< Tphl(NOR)
Click to expand...

this is incorrect. NOR should be faster than NAND in this case assuming tr sizes are the same.

if you wonder why NAND is faster than NOR in general, look at the transistor level circuit, and check the mobility of electron and hole.
 

NOR gate transistor level CMOS circuit has PMOS in series from Vdd to output. Mobility of holes is less than mobility of electrons. So, the output load, which is capacitive takes a longer time to charge. If , to compensate for the lower hole mobility, the width of the PMOS devices are increased, then, 1. The gate will consume more area. 2. The bigger PMOS will add more capacitance.
 
because nand gate density is more then nor gate density
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top