soloktanjung
Full Member level 6
Hi,
I need help regarding multiple clock synthesis using Synopsys Design Compiler.
My design has 2 blocks, clk1 for block1 and clk2 for block2. The clocks are independent each other and generate from different source from outside chip. How can I synthesis the design?
I tried to synthesis it by creating 2 clocks, setting the constraint for both clock independently, but the report_timing showed both clocks are dependent each other, which is launch clock is clk1 and captured clock is clk2.
I dont know it is correct or not. Can someone verify me please?
This is part of the report_timing:
Thank you in advance.
Hairo
I need help regarding multiple clock synthesis using Synopsys Design Compiler.
My design has 2 blocks, clk1 for block1 and clk2 for block2. The clocks are independent each other and generate from different source from outside chip. How can I synthesis the design?
I tried to synthesis it by creating 2 clocks, setting the constraint for both clock independently, but the report_timing showed both clocks are dependent each other, which is launch clock is clk1 and captured clock is clk2.
I dont know it is correct or not. Can someone verify me please?
This is part of the report_timing:
Code:
Point Incr Path
--------------------------------------------------------------------------
clock clk1 (rise edge) 27.00 27.00
clock network delay (ideal) 2.50 29.50
...
...
...
data arrival time 32.70
clock clk2 (rise edge) 28.00 28.00
clock network delay (ideal) 2.50 30.50
...
...
clock uncertainty -0.20 30.30
library setup time -0.17 30.13
data required time 30.13
--------------------------------------------------------------------------
data required time 30.13
data arrival time -32.70
--------------------------------------------------------------------------
slack (VIOLATED) -2.57
Thank you in advance.
Hairo