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Verilog syntax question

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farklempt

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What does -: and +: mean inside a vector definition
such as:
data[32 -:8]
data[32 +:8]
 

data[32 -:8] -> data[32 : 25] 8 bits starting from bit nr. 32 DOWN
data[32 +:8] -> data[32 : 39] - " - UP
 
maybe I'm wrong
but I think data[32 +:8] does give
data[39 : 32] not data[32 : 39]

at least when data was defined as
reg [39:0] data;

regards
 
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    j_andr

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qieda said:
maybe I'm wrong
but I think data[32 +:8] does give
data[39 : 32] not data[32 : 39]

at least when data was defined as
reg [39:0] data;
Click to expand...

you are right, my mistake;
J.A
 

but I think data[32 +:8] does give
data[39 : 32] not data[32 : 39]

at least when data was defined as
reg [39:0] data;
Click to expand...

It's wrong. Why don't you refer to the Verilog specification, it has clear examples for indexed part select syntax (in IEEE Std 1364-2005, 5.2.1 Vector bit-select and part-select addressing):

Code: 
big_vect[ 0 +: 8] // == big_vect[ 7 : 0]
big_vect[15 -: 8] // == big_vect[15 : 8]
little_vect[ 0 +: 8] // == little_vect[0 : 7]
little_vect[15 -: 8] // == little_vect[8 :15]

You see that +: always involves index numbers above the start value.
 
Had to look up the declaration of big_vect and little_vect...

Code: 
reg [15:0] big_vect;
reg [0:15] little_vect;

big_vect[ 0 +: 8] // == big_vect[ 7 : 0]
big_vect[15 -: 8] // == big_vect[15 : 8]
little_vect[ 0 +: 8] // == little_vect[0 : 7]
little_vect[15 -: 8] // == little_vect[8 :15]
 

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