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usage of set_timing_derate in Design Compiler

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subhash_chevella

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Hello,

Can one explain how set_timing_derate command in DC/PT will effect the design?
Why this command is used while doing timing analysis?
How it is related to process variation?
Can anyone explain about this in detail?

thanks & regards,
Subhash
 

you could add margin on clock network for example.
if you do not have the right PVT, you could add set_timing_derate for check on specific element. I did it for rom instance which we have a lower and higher PVT, but not the "middle" point. We have used th set_timing_derate for this, with success, the silicium works fine.
 

Hi rca,
thanks for your reply.
in your reply, "if you do not have right PVT" means?
Where do I find this? Can you explain in detail?
and actually I want to know that, how this constrain effect the design?
 

if you target PVT is wc_1v00 and you have only the wc_0v80 or wc_1v30 liberty files, you could load thewc_0v80or wc_1v30 and apply a timing derate to be "like" wc_1v00.
Then the tool will read the timing information from the wc_0v80 liberty and apply the timing derate coefficient to "obtain" the new timing information of this specific cell/macro.
I did it for a rom memory which we don't have the correct PVT corner. you could applied a different timing derate for the setup or hold timing.
 

When you don't know the exact PVT variations but still you want to observe what impact it would have on the timing then you can specify derate factor.....Is it right?

Regards,
Vid31
 
The process variations means that say u have two similar AND gates in ur design placed at diff places. Then ideally it should have same delay right. But due to process variations it will not be the same. also u can think the temperature variation might also be diff at these places.
So to be realistic we derate the values and check at the worst case possible for meeting the timing.

Hope this helps u in understanding.
 

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