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Characterization and Synthesis with T flipflop

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eklikeroomys

eklikeroomys

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Halo,

I have designed and characterized a T flip flop using Encounter Library Characterizer, and a .lib file was generated without any errors.
However, RTL Compiler is unable to use the flip flop for some reason. I have written a small piece of VHDL to exactly mimic the function of the flip flop, but RTL refuses to recognize it as adequate.
Has anybody had a similar problem or perhaps a solution?

Thank you!
 

during the synthesis, the tool replaces your code with a logic that provide a "better" solution? perhap in term of timing or area.

could you check which std-cell are used to generate your code?
 
No, I have limited the .lib file to contain only the T flip flop, an inverter and a two-input nand gate. This should be sufficient for synthesizing the simple design that I have written for test purposes.
The rest of the library has been separated for the time being, in order to force the tool to use the T flip flop.
The tool fails before it can do a mapped synthesis and gives the following error:

Error : Unable to map design without a suitable flip-flop. [MAP-2] [synthesize]
: Instance 'counter_reg' requires a simple flip-flop.
: Check the libraries for necessary flop cell. The cell could be marked unusable.
Synthesis failed.
Failed on synthesize -to_mapped
 

1-you could try to instantiate the cell in your code, and check if the timing are correctly seen by the synthesis tool
2-it will be great to check the functionality seen by the synthesis tool.
3-could you share with us the code to reflect the toggle flop?
 
Synthesis tool is a software, and doesn't work as human does.
I remember I read somewhere that some synthesis tool requires to have a certain type of cells in the library regardless of the design you have.
 
This is the piece of VHDL code that I am trying to synthesize:

if clk'event and clk='1' then
if enable='1' then
counter<=not counter;
end if;
end if;

It is the exact function of the toggle flipflop as well.

---------- Post added at 08:47 ---------- Previous post was at 08:42 ----------

I know that the synthesis tool absolutely requires at least an inverter and a two input nand/nor/and/or gate for synthesis. I have given the tool these cells along with the T flip flop which I want it to use. Unfortunately the tool wont use this cell and requires a simple flip flop. The T flip flop would be the most efficient option concerning area.
 

the following thread Forum/Digital Design and Programming/PLD, SPLD, GAL, CPLD, FPGA Design / VHDL code for a T-Flip Flop provides a vhdl code for T flop.

you code need to act on the counter signal by enable.

look at this thread, it seem "better".

---------- Post added at 09:06 ---------- Previous post was at 09:05 ----------

(sorry I don't know how to make link in responce, some one could explained)
 
Thank you guys, I seem to have gotten it working by simply adding another "simple" flip flop to the .lib file. RTL Compiler now uses the T flip flop for synthesis!
 

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