Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Clock uncertainty in Synthesis and static timing analysis.

Status
Not open for further replies.
V

vid31

Junior Member level 2
Junior Member level 2
Joined
Mar 10, 2011
Messages
23
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,412
Hi,

I have started working on STA and Synthesis.

Can anyone help me how to predict values of clock uncertainty,clock transition,input transition,input/output delay,etc.?


I know that it depends on design as well as clock frequency but is there any relation between these values and clock period like clock uncertainity is 4% of clock period?
 

Every company has their own deisgn flow and design margin according their libarary.

So. If you want to do synthesis or pre-layout STA, you must follow that margin guider, for example, ZWLM, 55% clock cycle as shrink ratio.
And for input/output delay, you can make it tighten enough in order to make STA result better.
 
  • Like
Reactions: vid31

    V

    vid31

    Points: 2
    Helpful Answer Positive Rating
Hi,

I'm also searching for that. I read in one tutorial in the internet that they use charaterize command in DC or refer to the datasheet for set_input/output_delay value.

Hairo
 
  • Like
Reactions: vid31

    V

    vid31

    Points: 2
    Helpful Answer Positive Rating
Thanks,

Hairo, would you provide me that tutorial....

Thanks,
Vid31
 
Last edited:

The clock uncertainty should also contain the jitter, if the clock generator is made by a collegue, just ask him the specification.
The duty cycle could also impact if you use both edges flip-flop design, from rise to fall and fall to rise, that "overconstraint" the clock max frequency if the duty cylce is 45%/55%.
 

@ rca,

but what value should be provided to overconstraint for 50% duty cycle clock?
Is there any convention in that?

Thanks,
vid31
 

Normally for i/o delays they do budgetting. Like say 70-30 if u dont get these from the top level designer.

Uncertainty would not be more than half cycle of ur clock. so max 50% of ur clock.

Clock transition u can set diff values and check how is ur insertion delay and skew. This value must be within the min and the max transition values.
 

Hi Vid31,

This is the tutorial I mentioned. Hope it helps you.

Best,
Hairo
 

Attachments

  • Synthesis-flow.pdf
    3.1 MB · Views: 263
Hi,

Does anyone know how to generate list of registers those are clocked by perticular clock?

I want the list of registers per clock domain.

Is there any command in design compiler?

Regards,
Vid31
 

Hello,

all_registers -clock <clock_name>
 
  • Like
Reactions: vid31

    V

    vid31

    Points: 2
    Helpful Answer Positive Rating
Hi oratie,

Thanks...
Thank you very much..

Regards,
vid31
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top