question about report_area command

Hi,guys,would you help me sth. about report_area command ,thx.
I synthesized the can bus RTL in Design Compiler,and set the target_library "gtech.db".I didn't involve any constraint while compiling and after finishing the compile, the information read:

****************************************
Report : area
Design : can_top
Version: C-2009.06-SP1
Date : Wed Sep 7 15:22:30 2011
****************************************

Library(s) Used:

gtech (File: /home/rockybc/eda/synopsys/dc/dc_2009/libraries/syn/gtech.db)

Number of ports: 33
Number of nets: 902
Number of cells: 810
Number of references: 68

Combinational area: 0.000000
Noncombinational area: 0.000000
Net Interconnect area: undefined (No wire load specified)

Total cell area: 0.000000
Total area: undefined

Information: This design contains unmapped logic. (RPT-7)
1



The report told "Total cell area: 0.000000".Why the cell area is 0, because of the gtech.db target_library or because of none constraint?Also ,why the information read "This design contains unmapped logic. (RPT-7)".
I am a newbie in using the EDA tool ,so please help ,thx

I think it's because of GTECH cell. Try mapping it to std cells and you'll see a real area.

Tools can estimate cell area from the information stored in standard cell library. When certain cells (or all cells) are unbound/unmapped, its impossible to estimate combined cell area.
Bind the design to std cell library and try again.

OK,thanks,i would try. By the way, would you tell me how to see the information about the equivalent gate count when the RTL code translates to the gate or cell related to gtech.db library(not related to the target library from foundary)?

gtach is the internal cell lib for DC. DC uses it to elaborate design. This means two points:
1. gtech cells do not have any practical meanings (area, power, delay, etc.) expect for their logic functions.
2. the logic described by gtech is the most complicated one (it is before optimization)

To see the area consumption of a design, you must link a practical cell library and optimize your design to the practical cell lib (as the target library)
The equivalent gate count is the total area of the design after mapped to the target lib divided by the area of a NAND2X1 gate in the target library.

As you can see, the gtech lib do not have area info. you cannot do the division.

I see, thanks all!