Differential Pairs Length Matching

Correct me if I'm wrong but 0.5mm equates to about 3.5pS delay!

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Yes. High speed standards like SATA allow e.g. for a intra pair skew of 10 to 20 ps, although the data rate is much higher.

Hi nelsonys,
I dont understand your problem with different trace lengths of your diff-pairs.
Because it is practically so to ca. 100% to eliminate if you will change both traces, the left one with the right one (of course in the same diff-pair)!
Check or validate my idea with both diff pairs in the relativ midlle of the diff groups on the before me linked xxx.bmp image... (27-05-11 06:06)
Or more better, refer pls to Buenos`s script too: https://www.edaboard.com/threads/211978/
Its only a bad guiding of the signal lines, simplest to correct that trough a changed placing
Greetings!
K.

Thanks FvM and Marce for detail explanation and helping hand on this matter.
It's good to have positive discussion on technical matter on the forum indeed.

For stripline case, 0.5mm approximately equates to 3.5ps.

Refer to the book "Signal Integrity and Printed Circuit Board Design" by Douglas Brooks, Chapter 14:
"The reason differential traces must be of equal length has almost nothing to do with signal timing. It has everything to do with the assumption that differential signals are equal and opposite and what happens when that assumption is violated .... Uncontrolled ground currents start flowing that at the very best are benign but at worst can generate serious common-mode EMI problems."

And according to "PCB Design for SI and EMC of Gb/s Differential Transmission Lines" by Keith Armstrong as posted by Marce, a differential skew as large as 80ps (part of factors of imbalance differential pair) worsens EMC and SI.

In view of these, one conclusion can be deducted that timing difference does not cause differential signalling to deteriorate, it's the imbalance that causes the differential signal to act like a worsened single-ended line, under high-speed condition, with widened return loop, causing emission eventually.

Length difference tolerance needs to be <1/10th of the signal's rise/fall time, so for my case, as stated by FvM, it is indeed been overcompensated. I doubted why our circuit designer proposed such harsh value to adhere to.

One thing I do not really understand in the notes from Keith Armstrong is that the serpentine routing causes "unbalanced trace pair", as in unbalanced coupling??
Say if the pin assignment hardly achieve balanced condition, what else can we do to balance the length of the pair besides using serpentine routing?
Is there a trade-off happens in this area, for eg. by consistently maintaining the coupling of trace pair and giving up of length mismatch??

Thanks!

I found another article that's worth for reference:
Length matching for high-speed differential pairs: loops and serpentines can add length to eliminate imbalance in your differential pairs
https://pcdandf.com/cms/images/stories/mag/0502/0502strategies.pdf

:grin:
Welcome to PCB design! Compromise is the name of the game, and the reason why a lot of us now have signal integrity, EMC, thermal, power system integrity tools:-(
A true diff pair should match exactly, but as you have experienced , when it comes to the reality of laying them out, its not always easy to get the desired results.
I use pin swapping (in conjuction with a rules set for the device in question) and try different ways of fanning out from the BGA to achieve the best possible result. I also strive for fig 4. type routing in the document above.

Interesting discussion here.

How's your option regarding very high-speed signal, e.g. more than 10Gbps with serpentine routing?

leekc_84 said:

How's your option regarding very high-speed signal, e.g. more than 10Gbps with serpentine routing?

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What are examples of such speedy interfaces? I don't know it. I'm not familiar with modern 40G-100G technology but i estimate that all this speed is divided into one or more lanes like in PCI Express. Real speed is then much slower.
At so high frequencies we can't do any srepentines because any additional length is additional loss in signal. Generally we will need microwawe techniques to route such signals tomorrow...