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[SOLVED] [MOVED]Questions about CPU architectures..

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romel_emperado

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Hi I have question about this terms

RISC, CISC, Harvard architecture and Von Neumann architecture.

I have already read that all in google. :) but I have doubts.

8bit PIC are RISC and 8BIts 8051 are CISC right?

my question is what is the relation of Harvard architecture and RISC or all of them.. sorry I dont know how to ask this in proper way :)
 

Re: Questions about CPU architectures..

The design of a Von Neumann architecture is simpler than the more modern Harvard architecture which is also a stored-program system but has one dedicated address and data buses for memory, and another set of address and data buses for fetching instructions.

The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.
 
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Re: Questions about CPU architectures..

yes.. thanks but I read about that.. and what are those RISC, CISC? I knew also it's an architecture.. let me ask you a specific question.. does Harvard architecture used in microcontroller? or RISC, CISC used in PC?
 

Re: Questions about CPU architectures..

harvard architecture is used in 8051 controller.
PC processor is CISC.

PIC is RISC.
 

Re: Questions about CPU architectures..

PIC is Neumann architecture
 


Re: Questions about CPU architectures..

It should be noticed, that a true Harvard architecture involves separate data and code data busses, not only separate memory spaces. While this criterion is clearly met for the PIC processors, it isn't for the 8051 family, which uses a common bus for data and instructions.

A more detailed discussion of modified Harvard and other hybrid architectures: Harvard architecture - Wikipedia, the free encyclopedia
 

Re: Questions about CPU architectures..

FvM said:
It should be noticed, that a true Harvard architecture involves separate data and code data busses, not only separate memory spaces.
Click to expand...
Exactly.
Many people misunderstand what Harvard arch is.
Separating the caches and TLBs is a consequence to maximize the performance out of Harvard arch, but not a harvard arch itself.
 

Re: Questions about CPU architectures..

FvM said:
It should be noticed, that a true Harvard architecture involves separate data and code data busses, not only separate memory spaces. While this criterion is clearly met for the PIC processors, it isn't for the 8051 family, which uses a common bus for data and instructions.

A more detailed discussion of modified Harvard and other hybrid architectures: Harvard architecture - Wikipedia, the free encyclopedia
Click to expand...


HI,

I've got now a question, I know PIC is RISC and you said it is harvard Architecture. now, the question is the RISC is part of harvard architecture? or RISC is a subset of harvard architecture? this is what I am trying to understand after reading it all in wiki ;)


IM thinking about ( RISC <--> Harvard ) and (CISC <--> Von Neuman) ...
 

Re: Questions about CPU architectures..

romel_emperado said:
HI,

I've got now a question, I know PIC is RISC and you said it is harvard Architecture. now, the question is the RISC is part of harvard architecture? or RISC is a subset of harvard architecture? this is what I am trying to understand after reading it all in wiki ;)


IM thinking about ( RISC <--> Harvard ) and (CISC <--> Von Neuman) ...
Click to expand...
They are not related each other.
RISC/CISC is based on instruction set architecture, and harvard/princeton arch is based on microarchitecture(implmentation).
You can make a RISC processor with either of princeton arch or harvard arch. The same for a CISC processor.
 
Last edited:

Re: Questions about CPU architectures..

lostinxlation said:
They are not related each other.
RISC/CISC is based on instruction set architecture, and harvard/princeton arch is based on microarchitecture(implmentation).
You can make a RISC processor with princeton arch, or a CISC processor with harvard arch as well.
Click to expand...

Thanks so much..
It's more clearer now... it is stated here also


Microarchitecture - Wikipedia, the free encyclopedia
 

Re: Questions about CPU architectures..

You will also notice that in RISC systems, rather than have many different instructions to manipulate data between registers and I/O, there are fewer instructions (hence RISC) but each has a reserved group of bits to identify the source and destination of the result. There are fewer instructions but more variations of them.

A good comparison would be to look at the instruction set of the 8085 with over 100 instructions and the PIC 16F628A with only 35. Note that the 8085 has 8-bit wide instructions while the PIc has 14-bit wide ones.

Brian.
 

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