[SOLVED] diffrence between the pins of QFP and dip microcontroller

Why does the
QFP package have
more pins than the DIP
package in microcontroler(such as atmega8)?

because the QFP has physically more pins

I konw that the QFT has more pins than DIP, i want to know why? because it has 2 GND and VCC more,why?its teacher's question

I don't understand the question, QFP package standard has more pins available so more pins can be wired out.
QFP has pins in all four sides instead of just in two sides and the pins are also closer together.

Alex

I agree with Alex. The ultimate reason is most likely in the trivial fact, that the commonly used QFP or TQFP package have more pins.

Technically, it's advantegous to have more GND and VCC pins. The DIL packaged processors mostly follow the old rule to use as few pins as possible to save board space. ATmega are somewhat modern in using at least two GND pins in the DIL version. But designers have learnt, that two is still poor in terms of digital and analog signal quality. So they took the opportunity to improve this point when changing to QFP package.

Current used to charge up the parasitic capacitance of transmission lines to logic 1 and then discharge it to a logic 0, must pass through the lead inductance of the IC power leads. These current transients develop voltage spikes across the lead inductances. These voltage spikes drive the internal power rails away from their respective values on the PCB. These voltage spikes appear on every signal lead connected to the IC. Vcc and Ground bounce are caused by switching transients. They appear due to high package lead inductances or inadequate power system decoupling or both. Worst case Vcc and Ground bounce occurs when all members of the largest bus switch from one logic state to the other simultaneously.

Click to expand...

One of the methods for managing these transient problems are using multiple GND and Vcc connections by minimizing the lead inductance of the IC power leads.


https://www.altera.com/literature/wp/wp_grndbnce.pdf

This is basically to eliminate the power and ground bounce in the chips, due to rapid signal tranisitions. Having very short leads or practically no leads reduces the inductance of these pins. As the inductance is reduced, the voltage developed due to V = L(dI/dT) effect, is reduced. Also imagine, many logic pins switching simultaneously and the current flowing through the GND or VCC pins at the same time.This, would have a high di/dt, which in turn, would increase the voltage across these VCC and GND pins. As, your voltage levels are referenced to ground, this would result in the logic pins, seeing a voltage different from what it should actually be. Having multiple GND and Vcc pins, results in currents dividing between appropriate paths, reducing the voltage developed or seen at a single pin.

Check out Digital Design by John Wakerley for an effective and detailed example.