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starting with AMBA AHB

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shaiko

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Hello people,

I'm in the process of learning about ARM's AHB AMBA bus.
My goal is to integrate existing VHDL designs on a single SOC's.
I've read the AMBA 2.0 specs and there're quite a few things that aren't clear to me.

First question:

How many addresses does a single AHB slave have? The address width is 32 bits, and if each slave answers to a single address - why do we need 4,294,967,296 addresses? Surely we aren't going to have so many cores on a single IC...

Please help.
Shai
 

Hi Shaiko,

Yes you are right, it doesn't immediately make sense to have that many addresses. But, keep in mind that AHB support bridges to other different bus architecture (APB, AXI comes to mind) and sometimes it is easier to carve up the AHB address space using only the a few bits at the top (to keep address decoding cost down).

narfnarf
 
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    shaiko

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Hello narfnarf,

Thanks for your response!
What exactly do you mean by "carving up the address space"?
 

When you create an AHB bridge to another bus, you have to dedicate a portion of the address to the new alternate bus system. For e.g., for some reason you have 2 AHB bus system (maybe b/c you have two CPUs), and you want CPU1 to talk to the slave of CPU2. One way to do this really easily is to dedicate a portion of CPU1's address space and map it directly to CPU2 devices. This is kind of my hand-waving explanation of carving up the address space...

narfnarf
 
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    shaiko

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I understand.
What about a simple master to slave transaction?

Suppose an I2C slave is implemented as an AHB slave (not APB).
From my understanding the transaction will proceed as follows:

1. An AHB master checks his HREADY input (from the HREADY mux). If it's '0' he can do nothing. If it's '1' he can start the transaction (step 2)
2. The initiating master puts the 32 bit I2C peripheral address on HADDR and the HWDATA on the next rising edge.
3. The slave sees that it's being addressed, gets the data from HWDATA and starts his "I2C assignment".

what happens next?
Must the HADRR address remain stable?
Does the slave lower the HREADY signal until it finishes the "I2C assignment"?

Shai
 

AHB does not works with single addresses.. it is suposed to to work with address spaces.... basically a slave will be mapped on some range of the address.. and usually the write and read operations are bursts with incremental address...

Imagin some slave that is mapped from 0x00000000 to 0x000000FF ... so... if a master wants to read from 0xA0 to AxA8 it will first send the adress 0x000000A0 with a read command, them every cycle increment 4 on the address.. til reaches 0x000000A8.. the slave maped on this raange will return a DWORD for every address...

This is done this way in order to make the peripherals be mapped on the processors memory, as the RAM is...

Most of the shared bus on processors have this sort of behavior.. take a look at PCI bus is almost the same....

Cya
 
Thanks Cya, this is helpfull.

I don't understand why the slave needs to have an HREADY input (and not just output).
A slave cannot initiate transactions, so why does it need to know when the bus is free?
 

Take a look at AHB specifications... everything is well explained there... anyway it is specified that a slave must sample the address and control signals on the bus when HREADY is high... so when som other slave has finished its transaction...

Cya
 
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    shaiko

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Sink0 said:
Take a look at AHB specifications... it is specified that a slave must sample the address and control signals on the bus when HREADY is high... so when som other slave has finished its transaction...

Cya
Click to expand...

I've read the specs - I know that...but it seems redundant to me for the slave to have an HREADY input.

Why should the slave care if the bus is free or not?
A slave can only answer to a master call and can't initiate transactions by itself.
Therefore, I can't understand why it needs to know when the bus is free or not...
 

I have another question about a master to slave transfer on an AHB-lite bus:

Suppose, an AHB-lite master initiates a transfer to an AHB-lite slave.
If the slave can respond at once, everything goes fine.
But if it takes the slave many cycles to do the job, then the slave must issue an HREADY='0' for as long as it's busy - This action would cause a bus lockup for a long period!

On a full AHB bus (not AHB lite) the way around it is using split transfers, but an AHB-lite doesn't support split transfers...Is there a way around a long duration lockout?
 

AMBA AHB interrupt support

Hello people,

I have a question about the AMBA AHB bus.
Let us consider the following simple scenario:

An AMBA master addresses an AMBA slave and sends him data to process.
It takes the slave some time to do the job, so the return data won't be available immediately...my question is:

Is there a way that the slave can let the master know when it finishes processing (like an interrupt). I want the master to be free to do other work and not have to poll the slave all the time.

Don't start new thread with the same content. Threads merged [alexan_e]
Click to expand...
 

Read the part about the RETRY and SPLIT transfers... the slave has the ability to tell the master that it does not want to transfer data now using the SPLIT/RETRY transactions. Once the master receives this transaction, it will have to re-arbitrate for the bus and try to read the data from the slave again. If the slave is ready with the data.. it will send.. else it can issue wait states or the SPLIt/RETRY again...
 

Sorry vlsi_whiz, you didn't understand my question.
Splitting the transfer won't help...
"Split" is an immediate slave response to a transfer initiated by the master - It comes right after the address phase and tells the master that it is busy and cannot send or recieve new data.

This isn't what I'm looking for!
What I need is a mechanism for the slave to tell the master know that it finished processing the DATA that he got from the previous transfer. (essentially an interrupt).
 

Hello people,

I have another question about the AHB bus:

When a slave returns from a split trasaction and issues the correct HSPLITx bit, what does it do in the next clock cycle?
Does it go directly to the data phase or back to the address phase?
 

This doesn't answer my question...

When a slave returns from a split trasaction and issues the correct HSPLITx bit, what should it do in the next clock cycle?
Does it go directly to the data phase or back to the address phase?
 

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