Mid rail Biasing of a differential pair

i am simulating a differential pair in CADENCE and having problems regarding the mid rail biasing and clipping . my amplifying pair is constantly biased at a voltage much higher than the mid range. Any suggestion regarding how can i ensure mid range biasing of my mos amplifying pair without effecting my gain, BW and other product values?

assuming u have a NMOS input with PMOS loads, the your output dc voltage should close the VDD ( it will be about VDD - Vgs(pmos) ), bcoz of the biasing. u can use a common mode feedback to bring it lower or size the PMOS with W/L <<1 to give it a large Vgs. this will affect your gain/bw. else u can use resistive load to get mid rail biasing at output.

need more details about ur specs to give u a better picture.

I think that knark's problem and question refers to the input of his amplifying stage and not at the output.Am i right knark?
CMFB slould be necessary for a fully differential implementation,is this your case?

One question : what you mean by saying "mid rail biasing"?Do you mean biasing at (Vdd-Vss)/2=(Vdd-0)/2=Vdd/2 assuming single positive supply?
If this is the answer and if the question indeed refers to the input,then you can bring the Vdd/2 CM input to the gates of the input pair with ideal Vdc sources in case that this is a university exercise or a standalone circuit/project/exercise.
In any other case you must see how your amplifier interacts with the previous stage,only in this way you will be able to determine the biasing of your input.

As steadymind suggested,give us more info and enable us to help you more ;-)

@jmilito the case is (VDD-0)/2: and i want this voltage Vdd/2 to appear as the dc output of my amplifier not my input !!! i want to do this to obtain maximum voltage swing !!!!! it is a differential pair with nmos amplifying pair and pmos active load pair !!!!! i am working on 240 nm technology !!!!! also once again just to be clear i want Vdd/2 to be my dc voltage output before applying any ac signal !!!!!!
@steadymind yes i have tried using the W/l thing sizing the mos in such a way so that Vdd/2 get dropped across my pmos load and hence i can obtain vdd/2 at the output of my diff amp. but this surely affects the gain bandwidth and also get me carried away far from my hand calculations and on to the hit and trial side !!!! well and i dont know much about the feed back technique and will like to hear about it !!!!!!
i hope i have elaborated my problem to sufficient extent!!!!!

Ok knark...things clearer now,yet you don't clarify if the amplifying stage is fully-differential or not.In case it is you need a CMFB to stabilize your common mode output potential (you can use an ideal model initially for your simulations and see how things work).

Start from the fact that your DC output must be set to Vdd/2.Then try to size your transistors,find bias current and bias voltages according to your specifications.
I would suggest that you leave hand calculations at the edge and try with simulations (trial and error as you said).
Apparently if you change the Vout,DC from the point that is now to a new point of Vdd/2,your circuit performance will change...Thus you need to do redesign to bring it back to a desired status.

Remember that in analog design you must make compromises among the various specifications you have to achieve.You lower the one,increasing the other etc...until you catch them all!