FPGA LUT to ASIC Gates

• Aug 5, 2004

• #1

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fpga gates lut relation

Hello all,

How to translate LUT to Gates?

If the ASIC product has 10k gates, how many LUT will the FPGA have?

I have read a paper on a decoder fulfill by ASIC, the decoder said it needs 30k gates, how many LUT will the FPGA have?

Regards,

Davy Zhu

 

• Aug 5, 2004

• #2

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gaonkc

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lut gate count

no , asic gates < fpga LUT becase in LUT many of gates can be implemented.

 

• Aug 5, 2004

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edavio

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fpga luts

normally, people count 1 LUT as 4 asic gates.

 

• Aug 5, 2004

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Big Boy

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fpga lut

It's hard to compare. When an FPGA give a number of gate, it's really a rough estimate.

A LUT can combine up to 4 inputs to give a single output. Plus, in an FPGA, the LUT are not the only elements. For example, registers (flip-flop) can account for a few gates in an ASIC.

The is really something that depend on the specific project. The best way to really know is to synthesize for FPGA, then see, after the mapping, how many logic blocks are used. Then, you can know what range of FPGA are optimal for that project.

Roughly, if the design is 30K gates, it should fit without problem in a 50K gates FPGA. But then, that depend on the applications. Remember that gates are only an estimate on FPGA, which assume that you use some % of your FPGA as distributed RAM for example.

 

• Aug 5, 2004

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it_boy

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converting from fpga luts to asic gates

It is not easy to find the equivalent gate count of a LUT without the knowledge of the design.
Fpr example, if you design a 4 input LUT as a 4 input gate/mux, the gate count may vary between 1 - 9. At the same time, if the LUT is designed to be a 16 bit RAM/ROM, gate count will be equal to or greater than at least 64.
Even the xilinx and Altera tools do approximation while presenting the equivalent gate count for a specific designSo in my opinion, it is not appropriate to calculate gate count for FPGAs.

 

• Aug 6, 2004

• #6

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ydao

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lut to gates

it is not easy to find a general way to find the equvalent gate count.

 

• Aug 6, 2004

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cawan

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xilinx equivalent asic gates

There are no standard definitions for asic gate to lut equalization. Anyway, the architecture of lut (4 fan-in and 1 fan-out) can provides quite a number of combination for types of logic design. Some more the implementation of lut can reduce the in circuit delay within the lut through the sram base technology.

 

• Aug 6, 2004

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Aser

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lut asic area

In the Xilinx library Unisim
there are all the equivalent models
for LUT images.
They are: AND2, AND2B1,AND2B2, etc.
They substitute the LUTs in the back annotation models.
You can do it as Xilinx does.
Then you can measure AND2 as 1 gate, AND3 as 2 gates, XOR as 4 gates, etc, and calculate all them together.
But FPGA gates measured by Xilinx tools besides
take into account Flipflop gates, memory gates, multiplexers, etc.
All of them are usually underloaded.
As a result for example, i8051 microcontroller which occupies 7500 gates in ASIC
in FPGA occupies ca. 35000 equivalent gates and ca. 1800 LUTs.

 

• Aug 6, 2004

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asic gate equivalent lut

These documents may help
**broken link removed**
https://www.xilinx.com/bvdocs/appnotes/xapp059.pdf

 

• Aug 11, 2004

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hunter694

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asic lut

From experience I wuold say that if you are designing a board and you have some idea of ASIC gatecount you should give it a 1:10 margin to be on the safe side. changing the fpga on a board can be pain ful

Hunter

 

• Aug 13, 2004

• #11

Arthurzss

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asic gates

I think use different tools to synthesize it and read the report will help you.

 

• Aug 13, 2004

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silencer3

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4-input lut equivalent gate count

I have seen a calculation from FPGA device to ASIC gate count ina forum. that is a nice table. and it is almost accurate.

 

• Aug 19, 2004

• #13

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silencer3

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xilinx convert lut to basic gates

this doc gives on how to convert from fpga gates to asic gates.

for further info pls contact the specific device vendor through proper channle