KR-500
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Hello,
i'm new to FPGA programming and now I've got a big problem. I already used the forum search but i couldn't find something useful
I'm using Verilog with the Spartan-3e board and Xilinx ISE Webpack 13.1. I tried to program a simple runnig light but there were several warnings so i reduced the code to a minimum but it still got those warnings:
I know that he sets my output to a constant value but i don't know why he does it. Here's my code:
The timer-modul works fine, i already tested it. I can't see the mistake in my code, im just trying to keep the value of LEDs in idle_state. Thanks
KR-500
i'm new to FPGA programming and now I've got a big problem. I already used the forum search but i couldn't find something useful
I'm using Verilog with the Spartan-3e board and Xilinx ISE Webpack 13.1. I tried to program a simple runnig light but there were several warnings so i reduced the code to a minimum but it still got those warnings:
WARNING:Xst:1710 - FF/Latch <LEDs_0> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_1> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_2> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_3> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_4> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_5> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_6> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <LEDs_7> (without init value) has a constant value of 0 in block <my_wrapper>. This FF/Latch will be trimmed during the optimization process.
I know that he sets my output to a constant value but i don't know why he does it. Here's my code:
Code:
module my_wrapper(
input In0,
input In1,
input CLK_50MHz,
input ROT_A,
input ROT_B,
input ROT_CENTER,
output [7:0] LED_ctrl
);
//----------------------------------------------------- DCM-Modul ------------------------------------------------
wire CLK_DV; // divided clock
wire CLKIN_IBUFG;
wire CLK0; // unmodified 50 MHz DCM clock output
my_dcm dcm_inst
(
.CLKIN_IN(CLK_50MHz),
.CLKDV_OUT(CLK_DV),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG),
.CLK0_OUT(CLK0)
);
//------------------------------------------------ Timer --------------------------------------------------------
wire timer_done;
my_timer timer_inst (
.clock(CLK_DV),
.reset(1'b1),
.timer_start(1'b1),
.timer_done(timer_done)
);
//----------------------------------------------------------------------------------------------------------------
parameter init_state = 2'b00;
parameter idle_state = 2'b01;
parameter led_state = 2'b10;
reg [1:0] state, state_next;
reg [7:0] LEDs_next, LEDs;
always @ (posedge CLK_DV) begin
LEDs <= LEDs_next;
state <= state_next;
end
always @ (state or timer_done or LEDs) begin
case(state)
init_state:
begin
state_next = idle_state;
LEDs_next = 8'b10101010; // new value
end
idle_state:
begin
state_next = idle_state;
LEDs_next = LEDs; // keep old value
end
endcase
end
assign LED_ctrl[0] = LEDs[0];
assign LED_ctrl[1] = LEDs[1];
assign LED_ctrl[2] = LEDs[2];
assign LED_ctrl[3] = LEDs[3];
assign LED_ctrl[4] = LEDs[4];
assign LED_ctrl[5] = LEDs[5];
assign LED_ctrl[6] = LEDs[6];
assign LED_ctrl[7] = LEDs[7];
endmodule
KR-500