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[SOLVED] Error in model sim! please help!!

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jianhuachews

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Hi guys.. Can anyone help me to look at the problem..? Modelsim gave me this error on my test bench..

# ** Error: C:/Users/Chew/Desktop/columncounter tb.vhd(20): Signal "col_out" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.NUMERIC_STD.UNSIGNED.

While my program code can be compiled... i don't know what's wrong!!

program
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity column_counter is
port ( 
        col_out : std_logic_vector(3 downto 0);
        rst : in std_logic;
        clk : in std_logic
        );
end column_counter;

architecture Behavioral of column_counter is

signal temp : std_logic_vector(3 downto 0);

begin

process(clk)
begin
          if(rising_edge(clk)) then
          if(rst='1') then
            temp <= (0=> '0', others => '1');
          else
            temp(1) <= temp(0);
            temp(2) <= temp(1);
            temp(3) <= temp(2);
            temp(0) <= temp(3);
        end if;
      end if;
end process;


col_out <= temp;
    
end Behavioral;


Testbench
Code:
library IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity column_counter_tb is
end;

architecture behavior of column_counter_tb is
  --Inputs
  signal rst: std_logic:='1';
  signal clk: std_logic:='0';
  --Outputs
  signal col_out: std_logic_vector(3 downto 0);;
  -- clock period definitions
  constant clkperiod : time := 20 ns;
  BEGIN

  -- Instantiate the Unit Under Test (UUT)
  uut: entity work.column_counter port map(
      col_out => col_out,
      rst => rst,
      clk => clk);
  
   -- Clock process definitions
   clkprocess :process
   begin
        clk <= '1';
        wait for clkperiod/2;
        clk <= '0';
        wait for clkperiod/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
        rst <= '1';
      wait for 70 ns;    
        rst <= '0';
        wait for 140 ns;  
        rst <= '1';
        wait for 200 ns;  
        rst <= '0';
      wait;
   end process;
end;

Thanks in adv!
 
Last edited:

Is there a extra semi colon in this line in the testbench code?

signal col_out: std_logic_vector(3 downto 0);;
 
hi guys! thanks for helping out to spot the mistakes. I've declared it to "out" in the line of entity. and also i've removed the extra ";"

But it's still giving me the same error!
 

hi guys! thanks for helping out to spot the mistakes. I've declared it to "out" in the line of entity. and also i've removed the extra ";"

But it's still giving me the same error!

it works..in ISIM
when you edit it
 
hey sanju thanks for trying to compile it!! I had it written in another set of file with the exact same edited codes and it works... I wonder why.. Anw thanks a lot for the help guys!! :)
 

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