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cap/trans violations and DRC violations (using synopsys - IC Compiler)

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ee1

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Hi all,
i am new to ICC and would like to get some help in 2 issues:
i am now after post route and have 2 problems:
1. have ~ 100 transition violations and ~10 capacitance violation.
2. have ~450 DRC violations:
End of line spacing, Diff net spacing, Short, Fat wire via keepout enclosure, Special notch spacing, Less than minimum area, Diff net via-cut spacing, Edge-line via spacing, Same net via-cut spacing, Less than minimum edge length.

i wanted to know if there are any commands (with different flags maybe) that is worth try running before fixing them manually, i am asking for the cap transition and drc violations..

Many thanks.
 

You should try using "focal_opt". I think it'll take care of some max trans violations.
 
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    ee1

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DRC violations will be better fixed by changing the cell layout the notch errors are because of the irregular height of the layers in different cells
 
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    ee1

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Hi,

use focal_opt with drc_pins and drc_nets switches to fix your maxcap and max trans violations.
use can specify the violation as a file or as "all".


thanks.
 

thank you all!
 

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