fanwel
Full Member level 3
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Hi all;
Below is my code where I try to apply addition and division operation into single value of a vector. Below is my code:
Package my_data_types is
Type vector is array (7 downto 0) of integer;
Type vector_next is array (3 downto 0) of integer;
End my_data_types;
LIBRARY ieee;
USE ieee.ALL;
USE ieee.std_logic_arith.all;
USE work.my_data_types.all;
ENTITY adddiv IS
PORT (
Ra : IN vector;
clk : IN bit;
A : OUT vector_next
);
END adddiv;
ARCHITECTURE adddiv OF adddiv IS
type t_temp is array (7 downto 0) of integer;
BEGIN
Process(clk)
variable temp: t_temp;
BEGIN
If clk'event and clk = '1' Then
temp := (((Ra(0) + Ra(1))/2), ((Ra(2) + Ra(3))/2),
((Ra(4) + Ra(5))/2), ((Ra(6) + Ra(7))/2));
End if;
A <= temp(0 to 3) after 20ns;
END PROCESS;
END adddiv;
When I compile, this error occur:
Error (10381): VHDL Type Mismatch error at adddiv.vhd(29): indexed name returns a value whose type does not match "vector_next", the type of the target expression
Can anyone help me..Thanks
Below is my code where I try to apply addition and division operation into single value of a vector. Below is my code:
Package my_data_types is
Type vector is array (7 downto 0) of integer;
Type vector_next is array (3 downto 0) of integer;
End my_data_types;
LIBRARY ieee;
USE ieee.ALL;
USE ieee.std_logic_arith.all;
USE work.my_data_types.all;
ENTITY adddiv IS
PORT (
Ra : IN vector;
clk : IN bit;
A : OUT vector_next
);
END adddiv;
ARCHITECTURE adddiv OF adddiv IS
type t_temp is array (7 downto 0) of integer;
BEGIN
Process(clk)
variable temp: t_temp;
BEGIN
If clk'event and clk = '1' Then
temp := (((Ra(0) + Ra(1))/2), ((Ra(2) + Ra(3))/2),
((Ra(4) + Ra(5))/2), ((Ra(6) + Ra(7))/2));
End if;
A <= temp(0 to 3) after 20ns;
END PROCESS;
END adddiv;
When I compile, this error occur:
Error (10381): VHDL Type Mismatch error at adddiv.vhd(29): indexed name returns a value whose type does not match "vector_next", the type of the target expression
Can anyone help me..Thanks