Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

insertion delay and latency

Status
Not open for further replies.

pratap_v

Member level 4
Member level 4
Joined
Jan 6, 2007
Messages
71
Helped
10
Reputation
20
Reaction score
7
Trophy points
1,288
Activity points
1,688
insertion delay

Can anyone tell me the difference between the insertion delay and latency? I know that both are one and the same but in interview they asked me specifically this question. They asked why two terms if they have same meaning.
Thanks in advance
 

clock insertion delay

Dear dude,

Latency is the dealy between clock and clock elemented componeents

insertion delay- it is the delay where the data takes to flow into input pin.

hope i am right

phutane
 

difference between delay and latency

latency is the number of clock cycles data takes from input to output...
for example if you have a chip and after applying input the valid output is available after three clock cycles then it is said to have latency of three....

Increasing the latency of the circuit is called pipelining...

correct me if I am wrong....

Thanks

...........:D
 

what is insertion delay

insertion delay means delay due to clock buffer insertion during CTS
 

insertion delay

I guess they mean clock insertion delay and clock latency.
clock latency is concept of clock tree depth before CTS, which mean a estimated value. It can be a contraint of CTS.
insertion delay mean the clock tree depth after CTS.
 
as i understand it,
clock latency is the combination of source latency and network latency which is basically the amount of time it takes for the clock signal to reach the clock sink from the clock generation point. but the term latency is applied before the clock tree has been built and we are at the "ideal" stage wherein we need to apply these latency values to the design because the tool cant calculate the delays in the absence of a clock tree.

insertion delay is the same delay mentioned above, but now the clock tree has been built and we can propagate the actual delays.

so basically, the difference is that the latency values are ideal values that we give befire CTS and insertion delay is the actual values that is propagated after CTS.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top