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It depends on your application.
The simple bias circuit: resistor connected ground, another terminal of resistor is connected to a gate of diode-connected PMOS. The PMOS's source is connected to VDD.
The opamp is a load compensated folded cascode structure succeeded by a source follower which performs buffering and level shifting.
The opamp runs on a single 5 V power supply. The output dc level is 1.15 V. It is kept on this level with a standard type common-mode feedback.
The GBW of the opamp is 100 MHz, but because of the partial feedback the second nondominant pole is situated at only 30 MHz.
Questions:
1. Is there the two power supply +5v and -5v used for the circuit? The process is 1.2 micron CMOS.
2. What means partial feedback?
3. Do the resistor and capacitor in feedback effect on the design procedure?
4. By given information (DC level, GBW, Nondominant pole), how i design the transistors size?
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