Help with bidirectional interface of a FPGA with a uC

Hi need to implement a bidirectional 8 bit interface of a FPGA with a microcontroller. For now i am developing with a Ciclone II but i will have to make it for a Spartan-3A too.

Inside the FPGA i have 2 fifos one that will hold the data that i will wire to the uC and on the other i have to put the data that the uC sends to FPGA. The communication is controlled by the uC, so there will be a we pin to set the pins direction.. a 8 bit birectional data bus, a data_rdy pin to tell uC that there is data availabe on the FIFO, and a "clk" pin. I mean clock becouse it wont be a continuously clock. Just something like on every posedge the data will be sampled on FPGA (if we is asserted) or the FPGA will change the the output (if we is not asserted). On the FPGA there will be a 50Mhz clock. I am implementing both fifos using altera megafuntion (and probably the same will be done with Xilinx FPGA). I have a few questions. First will this code works to control the port direction? Or it should be clocked?


Second, i have two options to create this communication. First, to use the communication control pin to clock the FIFOs, but i dont know if need to use a constiguously clock on FIFOs ... The other option would be to synchronize all the signals to FPGA 50Mhz, and create a pulse on the wt_en and rd_en port of fifos on every edge of the uC ctrol pin.

Will both work? Anything i should pay attention?

Thank you!!

Hi, your code for bidirectional pin is correct and it shall work fine.
If you use quartus for designing this, you will have the bidirectional port present as an in-built component.
For your second question, both options should work fine.
Option 1: Async fifo operation and has better power reduction.
Option 2: Synchronous fifo operation.

Keeping data integrity despite of clock domain crossing is typically the most serious problem when designing a processor bus interface for a FPGA. If you plan to use a FIFO as data buffer anyway, you may want to implement it as domain crossing (DCFIFO).

Actually there was a mistake at my code. The data_in and data_out were with inverted directions as they are the fpga interface to the port. Anyway my problem is that the uC clock will have posedges when he want to write or read from the FPGA.. so it will not be continuously present. I am afraid a dual clock FIFO must have both clocks all the time to behave correctly (in special becouse i am using show ahead fifos). I could use use an extra pin to drive each enable port from each fifo separately, and create a clock on uC with a timer, but it is almost impossible to ensure a high speed synchronous operation on the uC. I will probably run some tests any way... Thank you for the help!!

Any other sugestion is welcome.

Internally, the databus activity of a µP is generated synchronously, but you may face the problem, that this clock isn't exposed to a pin. For maximum interface speed, it may be suitable to regenerate a databus clock in a special designed PLL. Or you have to sample the bus control signals with a fast clock, either a FPGA system clock, preferably the same clock that the FPGA side of the interface uses, then no domain crossing is involved. Or a separate clock in combination with a DCFIFO.