Steps needed to be taken care while doing Floorplanning

While doing floorplanning what needs to be taken care?How to proceed with the flooplannning steps in a sequence?

Hi friends,
May be the attachment will help u know some guidelines for better floorplanning
thanks,
Sowmya

question regarding module constraints type in floorplanning

HI all,

After placing Hard macros in core area we required placement blockage (halos). now I have question in module constraints type. If we are not pre-placed module in core area then we just place std.cell during placement. so someone will put some light when fence ,region and guide will come in picture..?
thanks in advance

why i can not donw load pdf file ????

fence,region and guide are used to guide the placment tool to place the module placement, so for this u should have done one pass of placement with out these constraints and after that placement only u can come up with area constraints for module placement

Hello sowmya,

you have any other documents related to the physical design please send...

What is Floorplan?

Die Size Estimation
pin/pad location
hard macro placement
placement and routing blockage
location and area of the soft macros and its pin locations
number of power pads and its location.

Note:- For block level Die size and Pin placement comes from TOP

Flyline analysis is required before placing the macros

While fixing the location of the pin or pad always consider the surrounding environment with which the block or chip is interacting.

This avoids routing congestion and also benefits in effective circuit timing

Provide sufficient number of power/ground pads on each side of the chip for effective power distribution.
In deciding the number of power/ground pads, Power report and IR-drop in the design should also be considered


Orientation of these macros forms an important part of floorplanning

Create standard cell placement blockage (Hard Blockage) at the corner of the macro because this part is more sensitive to routing congestion.


using the proper aspect ratio (Width /Height) of the chip


For placing block-level pins,

First determine the correct layer for the pins

Spread out the pins to reduce congestion.

Avoid placing pins in corners where routing access is limited

Use multiple pin layers for less congestion

Never place cells within the perimeter of hard macros.
To keep from blocking access to signal pins, avoid placing cells under power straps unless the straps are on metal layers higher than metal2
Use density constraints or placement-blockage arrays to reduce congestion
Avoid creating any blockage that increases congestion.