Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How can i measure inverter input capacitance in Hspice simulation?

Status
Not open for further replies.
Oveis.Gharan

Oveis.Gharan

Full Member level 4
Full Member level 4
Joined
Oct 21, 2006
Messages
197
Helped
34
Reputation
68
Reaction score
25
Trophy points
1,308
Location
Iran
Activity points
2,503
Hi everybody.

Is there anyone how can guide me to measure input parasitic capacitance with HSpice simulation?

Thanks in advance.
Alireza
 

Its easy to calculate the approximate capacitance by calculating the capacitance/um2 for the gate of a MOS and then multiplying by area, but you can probably get a good approximation by biasing the gate with a current source and then using: i=C.dV/dt to calculate the capacitance
 
Thanks for your answer.
What about output parasitic Capacitance of a Digital Gate such as Inverter?
Can it be measured with current source again?

Thanks.
Alireza
 

Im not sure about the output parasitic capacitance, there could be many causes, what do you need it for?
 
I want to model gate drivers in an interconnect configuration and set an analytic expression for Delay. That i need to model an Invertor as driver with internal resistor and in/out parasitic capacitors. Then there is no other way to evaluate the invertor parameters.

Thanks for your helpful attention.
Alireza
 

Im not sure about this, but you can possibly switch the inverter, then measure the average current at the output and use this with i=C.dV/dt to compute the capacitance
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top