Unbound devices in LVS checking

assura lvs unbound pin

Hi all,

I have a problem while running LVS with Assura 3.1.4. The LVS does not run successfully because of these errors:

Error: Device 'mimcap(CAP)' on Schematic is unbound to any Layout device.
Error: Device 'mimcap(Generic)' on Layout is unbound to any Schematic device.
Error: UnBound devices found.
Info: All devices must be bound or filtered for comparision to be run.

I only have one mimcap on my layout. It's a very simple layout. What is the problem here?

Thanks a lot,

Frank:?:

on schematic is unbound to any layout device

check your bind file. bind cap to cap you have binded generic.

unbound pin lvs

Currently all the content of my bind file (bind.vldb) are commented out. I have very little knowledge on this type of file. Would you please give me a hint about binding the component? Any document teach me how to do this?

cadence unbound pin

IF u r using cadence - assura verification tool.

go for LVS window.

in that " Netlisting Option" icon will be there.

if u click it another window will pop up.

in that select " Use model property as device name if model in instParameters"

after that click o.k and LVS

unbound pin

Check pin connection.

unpound pin cadence lvs

please refer to the assura command referrence

abortOnUnboundDevices abortOnUnboundDevices( [t | nil] )

Description
Allows you to control whether or not Assura LVS terminates a run when it encounters unbound devices and expandOnError(( reduce t)) or expandOnError(( match t)) is set. Unbound devices are devices that exist in either the layout or the schematic, but
not in both.
By default, when Assura LVS finds an unbound schematic or layout device, it issues a warning message and continues with the run. However, if you specify expandOnError((reduce t)) or expandOnError((match t)), Assura LVS exits with an error message, because under these conditions the potentially lengthy LVS run would not be able to match the layout and schematic.
When abortOnUnboundDevices is set to false (nil), Assura LVS reports unbound devices as in the following example and continues the run:
Error: Device ‘P(MOS)’ on Layout is unbound to any Schematic device.
When abortOnUnboundDevices is set to true (t), Assura LVS reports the unbound device
and an information message as in the following example and terminates the run:
Error: Device ‘P(MOS)’ on Layout is unbound to any Schematic device.
Info: All devices must be bound or filtered for comparison to be run.

extractdevice extractcap assura

wildgoat is right - first in your avCompareRules-setup bisable the "Abort On Unbound Devices" this will then let you continue running your LVS and gives you more idea on the real issue of your LVS problem.

assura lvs pin

In this specific case, what might have happened - device name remained same - just the device type mismatch has happened.

On Sch side - it is mimcap(CAP), versus on layout side - it is mimcap(Generic)

Either this 'mimcap' has been extracted from layout using extractDevice() command instead of using extractCap() - And at times that is legal and necessary for various reasons, it is done purposely to utilize strength/flexibility of generic device extraction.

There are several ways to address that mismatch issue:

1. adding a binding file usually mentioned as "bind.rul" please check, you might be already having one - shipped with the PDK you are using.
might be named as auLvs.bind or auCdl.bind (usage depends on schematic is in dfII or CDL/Spice )

Here "bind.rul" needs a line:
C mimcap(CAP) mimcap(Generic)

2. Convert generic device to standard device by :
2.a. using capDevice() command :
under layout netlisting syntax of avCompareRule
capDevice("mimcap(GENERIC)" )
2.b. Add namePrefix("C") or namePrefix("XC") of
course understanding full implication of its usage.

Hi all!
I have got the same problem with unbound pin after LVS cheking.
Error: Unbound pin sch||lay 3||0
Assura recognize vdd and gnd, but doesn't understand "in" and "out" pins.
Thank's in advance!
Alex.

Question is - are you asking Assura to read those pins from layout? Is this gds or dfII layout? check geomConnect for label command..
You need to understand how Assura makes PINs and | or named-nets, from text-labels, virtuoso-pins etc. Check command reference for textToPin(), pinText(), pinLayer() commands.
Check the file <runname>.erc, which will show - what labels assura was able to read, which x,y coordinate, and whether it was able to successfully assign that label to some interconnect layer, and whether it has become a PIN or lableled Net.

Re: assura lvs pin

sat said:

In this specific case, what might have happened - device name remained same - just the device type mismatch has happened.

On Sch side - it is mimcap(CAP), versus on layout side - it is mimcap(Generic)

Either this 'mimcap' has been extracted from layout using extractDevice() command instead of using extractCap() - And at times that is legal and necessary for various reasons, it is done purposely to utilize strength/flexibility of generic device extraction.

There are several ways to address that mismatch issue:

1. adding a binding file usually mentioned as "bind.rul" please check, you might be already having one - shipped with the PDK you are using.
might be named as auLvs.bind or auCdl.bind (usage depends on schematic is in dfII or CDL/Spice )

Here "bind.rul" needs a line:
C mimcap(CAP) mimcap(Generic)

2. Convert generic device to standard device by :
2.a. using capDevice() command :
under layout netlisting syntax of avCompareRule
capDevice("mimcap(GENERIC)" )
2.b. Add namePrefix("C") or namePrefix("XC") of
course understanding full implication of its usage.

Click to expand...

hi i have this problem with both pmos and nmos in layout they are generic and in schematic mos...
i have used gpdk090
version 4
tell me where to find these bind files i am new and dont have much idea where to find them.

What LVS avParameters and avCompare ruls must be set for pin's ???

I was facing the same problem with UMC65. lvs didn't pass with the same error of "unbound device...". The solution was to keep all the components separate from each other in layout. when there is an overlap the lvs cannot recognize which devices are used, thus it ignores one device.

I also have the same problem with UMC130nm.
The error message I'm getting is:

*ERROR* Device 'P_12_HSL130E(MOS)' on Schematic is unbound to any Layout device.
*ERROR* Device 'N_12_HSL130E(MOS)' on Schematic is unbound to any Layout device.
*ERROR* UnBound devices found.
Info: All devices must be bound or filtered for comparison to be run.

I've tried disabling the "Abort On Unbound Devices" rule check but still returns the same error (neither expandOnError(( reduce t)) or expandOnError(( match t)) is set). I don't understand this inconsistence between schematic and layout because I generated all devices by Gen from source command.
Please, help!

---------- Post added at 13:24 ---------- Previous post was at 13:18 ----------

I forgot to say that in the layout no psub-me1 via is available for connecting the bulk of the nmos to ground. So I used the pactive-me1 via and connected it to gnd. I don't know if this procedure is correct and if it can be the source of the error I'm getting...

Hi Kicchan,
Have you checked connectivity, against source? Also check/define mapping between layout and schematic components.

Hi babakta,

thank you for your reply.
My connectivity should be ok (it's a simple inverter just to check if my layout works with Assura). Where can I find this check/define mapping command? Everything looks fine, I really don't inderstand where the error comes from...:sad:

By mapping I mean Define Device Correspondence, under Connectivity menu in layout window. There you can see which devices are mapped between sch & layout. Also remember, in some cases even if the DRC is passed, but overlapping devices can cause confusion for LVS. Good luck

Thanks a lot, babakta.
Actually it says there are inconistencies between schematic and layout:

*ERROR* 'W' on source figure 'NM0' is 'iPar(\"effW2\")'
...on layout figure '|NM0' is '200n'
*ERROR* 'simM' on source figure 'NM0' is 'iPar(\"m\")*iPar(\"fingers\")'
...on layout figure '|NM0' is '1'
*ERROR* 'W' on source figure 'PM0' is 'iPar(\"effW2\")'
...on layout figure '|PM0' is '200n'
*ERROR* 'simM' on source figure 'PM0' is 'iPar(\"m\")*iPar(\"fingers\")'
...on layout figure '|PM0' is '2'

Notwithstanding, in my schematic the numbers are correct and correspond to the sizes I have in the layout. Why do my schematic numbers look like as if they are parameters??? :shock:

For clarity, I attach the schematic together with its layout and the discrepancies I've got.
Thank you again...

OK, in your current schematic just put numbers instead of parameters. make the life easier for Cadence ,OR create another version of your schematic(just copy the cell view to a new design) and in this new version, just give the actual numbers for devices in schematic.