Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

place_opt command - IC compiler (synopsys)

Status
Not open for further replies.

ee1

Full Member level 2
Full Member level 2
Joined
May 31, 2011
Messages
120
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,036
Hi all,
i have a question regarding "place_opt" command:
can the tool decide adding cells (buffers for example) in order to optimize the design? or it place only the cells that exists in the netlist ?

thanks!
 

place_opt does placement + optimization, so yes, it will add buffers in the design to fix design rule violations (max_cap, max_trans), add in buffertrees for high fanout nets, and to help fix timing violations
 
just to complete the shelby's answer, it could add or removed buffer/inverter is needed.
 
  • Like
Reactions: ee1

    ee1

    Points: 2
    Helpful Answer Positive Rating
Hi,

"place_opt" command places the stdcells present in the netlist and adds extra buffers, inverters for the optimization.
it even performs high fan out synthesis for all high fan out nets, excluding clock nets.
Clock nets are treated as ideal nets.
 
  • Like
Reactions: ee1

    ee1

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top