How to Increase DFT coverage?

Below is the Coverage report after testbench generation using tetramax tool. Now I want I would like to know how can I increase the coverage both Test as well as Fault coverage. Please take into consideration as I am new to DFT.


Collapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 7949078
Possibly detected PT 3174
Undetectable UD 98363
ATPG untestable AU 264100
Not detected ND 27303
-----------------------------------------------
total faults 8342018
test coverage 96.45%
fault coverage 95.31%
-----------------------------------------------

Inorder to decrease the ATPG untestable faults, try running Fast Sequential or Full Sequential ATPG Engines (Using run_atpg -fast_sequential_only or run_atpg -full_sequential_only commands). But Full or Fast sequential algorithms need more runtime as they are computationally intensive algorithms

To decrease the not detected faults, try increasing the abort limit (using set_atpg -abort_limit <N> command). Increasing the abort limit also increases the runtime. So incrementally increase the abort limit

If you want more clarification please revert

Hi!! thnks for d reply vivek .
But I am already using Fast Sequential and the abort limit is set to 4. How to go about it ?

Try running Full sequential and also increase the abort limit to 10.

I am not an experienced guy. Forum members pls help !!

Apart from these two options, is there any more solution to increase the DFT ??

Apart from increasing abort limit and running full sequential options..I would like to suggest these additional things.
1. study the warnings fast scan reported during drc and check if you can get rid of them by doing some modifications.
2. If you have many black boxes in your design, the coverage drops very significantly. Your AU fault number reads big, try to reduce that by getting libs of those black boxes if possible.
Let me know if this is useful or not !

if you could add wrapper aroung memories/analog module, to avoid unknowed state from this module, that decreased the coverage.
I believed you already control the gated clock and the reset

hi vishh,
Observe the non_scan_cells report. Look the reason for them.Sometimes the tool may exclude flops those are having issues with set/reset and gated clock from the scan chain. Try to fix them.

vivek_p said:

Inorder to decrease the ATPG untestable faults, try running Fast Sequential or Full Sequential ATPG Engines (Using run_atpg -fast_sequential_only or run_atpg -full_sequential_only commands). But Full or Fast sequential algorithms need more runtime as they are computationally intensive algorithms

To decrease the not detected faults, try increasing the abort limit (using set_atpg -abort_limit <N> command). Increasing the abort limit also increases the runtime. So incrementally increase the abort limit

If you want more clarification please revert

Click to expand...

Hi Vivek,

how fast sequential and full sequential ATPG will helpful to reduce the ATPG_Untestable faults?

can you please explain?

Regards,
Yuga

Hello,

Fast sequential and full sequential is help when there are so many non scan cells.
So first we have to check that how many non scan cells are there in between 2 consecutive scan flops. It there are so many consecutive flops with in between non scan flops, than we can go to increase the sequential engine.

AU faults means ATPG untestable, we have define some constraints, engine. Due to these constraints, engine, ATPG tool is not able to get coverage over there. By chainging the engine, we are removing 1 constraints (i.e. only 1 capture cycle), We can reduce the count of AU faults.

As earlier Vivek mentioned,
To reduce count of AU faults - Go for Fast or Full sequential engine
To reduce count of ND faults - Increase abort limits

--
Thanks & Regards,
Maulin Sheth

Thanks for the reply Maulin,

You mean to say that by increasing the sequential engine, The ATPG_Untestble faults will be reduced.

Other than this, Is any other solution to reduce the ATPG_Untestable faults.

Hello,

There are always multiple ways to reduce ATPG Untestable :
But most commonly 2 ways :
1. By using commands only.
2. By doing analysis.

By commands : use sequential engine.
By analysis :
- we have to generate the report for the AU faults, thereafter do the analysis.
- In TMAX, it generated the detailed verbose report for the analysis. It shows that the causes of AU faults. like on design test mode pin, we can never detect sa1. This is only 1 type. its shows the other types also. So other option is doing analysis only.
We can do analysis block by block also.

Thanks Maulin for your reply.